Single-Wire Bi-Directional Interface Clock Learning
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Solution Overview
Problem
Conventional single-wire bi-directional communication systems require a separate clock module for synchronized data transmission, which is complex and involves specific end signals, making them undesirable.
Innovation Solution
A method for transmitting clock frequency information through a single-wire, asynchronous communication system where the master device learns the clock frequency of the slave device by recognizing a distinctive waveform, allowing it to adjust its sampling and transmission rates for optimal data reception and transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate clock module is used for synchronized data transmission, then data transmission reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the clock synchronization function from a separate clock module and integrates it into the single-wire communication protocol. The master device generates clock signals directly from its internal clock without requiring a separate clock module, thereby reducing device complexity while maintaining synchronization reliability through protocol-based timing coordination.
Solution Approach 2:
The single-wire interface is designed to serve multiple functions: data transmission, clock signal transmission, and synchronization. By making the communication wire universal for all these purposes, the patent eliminates the need for separate clock modules and reduces overall device complexity while maintaining reliable synchronized operation.
2Measurement precision
If specific end signals are used in the communication protocol, then data transmission accuracy is improved, but protocol complexity increases
Solution Approach 1:
The patent employs periodic clock signals transmitted through the single wire to provide timing information for data transmission. These periodic signals serve as implicit synchronization markers that eliminate the need for separate end signals, reducing protocol complexity while maintaining data transmission accuracy through continuous timing reference.
Solution Approach 2:
The communication protocol incorporates feedback mechanisms where the master device adjusts its sampling rate based on the transmitted clock frequency information from the slave device. This feedback loop allows the system to automatically synchronize without requiring complex end signals, reducing protocol complexity while maintaining accuracy.
3Device complexity
If the master device uses a fixed sampling rate, then device complexity is reduced, but adaptability to varying slave clock frequencies deteriorates
Solution Approach 1:
The patent implements dynamic sampling rate adjustment in the master device based on the actual clock frequency transmitted by the slave device. The master device receives clock frequency information through the single-wire interface and automatically adjusts its sampling rate to match the slave's clock frequency, thereby achieving adaptability without significantly increasing device complexity through automated rate adjustment.
Solution Approach 2:
The system changes the sampling rate parameter dynamically according to the slave device's clock frequency. The master device measures the slave's clock frequency and adjusts its sampling parameter accordingly, enabling adaptability to varying frequencies while keeping the overall device architecture relatively simple through parameter-based adaptation rather than hardware changes.
Data Source
AI summary
A single-wire, bi-directional communication protocol is provided in which the sending device transmits its clock frequency and its bit transmission period and data through a predefined waveform pattern or “learning sequence” that is recognizable by the receiving device and in a period of time, as measured in number of sending clock cycles, that is known to the receiving device. By clocking the full length of the predefined waveform pattern using its own internal clock, the receiving device becomes aware of the bit transmission period of the sending device.