Single-Wire Clock Recovery via Embedded CPWM Encoding
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Solution Overview
Problem
Existing communication techniques require separate wires for data and sampling clock signals, which is inefficient and complex, often necessitating the use of complicated phase-locked loop (PLL) or delay-locked loop (DLL) circuits and training sequences to recover the sampling clock signal in one-wire or one-channel encoding methods.
Innovation Solution
The proposed solution embeds the sampling clock signal within the data signal in a single-wire serial bit stream using coded-pulse-width-modulation (CPWM) encoding techniques, allowing for clock recovery without the need for PLL/DLL circuits or training sequences, and employs a pulsed digital module and delay module to generate and recover the sampling clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate wires are used for data and sampling clock signals, then communication reliability is improved, but device complexity and wire count increase
Solution Approach 1:
The patent merges the data signal and sampling clock signal into a single transmitted signal by embedding the clock signal within the data signal structure. This allows both signals to be conveyed over one wire simultaneously, reducing wire count while maintaining the ability to recover both components at the receiver through signal processing techniques.
2Device complexity
If one-wire encoding techniques are used, then device complexity is reduced, but reliable clock signal recovery becomes difficult without PLL/DLL circuits
Solution Approach 1:
The patent segments the recovered signal into distinct data portions and clock signal portions by inserting known training sequences at regular intervals. This segmentation allows the receiver to independently process and recover the clock signal from the training sequences without requiring complex PLL/DLL circuits, simplifying the receiver design while maintaining reliable clock recovery.
3Measurement precision
If training sequences are used for clock recovery, then clock signal recovery accuracy is improved, but transmission time and efficiency decrease
Solution Approach 1:
The patent uses partial training sequences that are shorter than full training sequences would be, placing them at strategic intervals within the data stream. This partial approach provides sufficient information for accurate clock recovery while minimizing the time overhead, achieving a balance between recovery accuracy and transmission efficiency.
Data Source
AI summary
A system, apparatus, method and article to encode, clock recover, and sample data bits are described. The apparatus may include a pulsed digital module comprising a first clock input, a first data input, a data output, and a reset input. The first clock input to receive an encoded signal from a single-wire. The encoded signal comprising a serial bit sequence comprising a clock signal embedded encoded data bit. The pulsed digital module to capture an edge of the encoded signal at the first clock input in accordance with a logic level coupled to the first data input. A delay module comprising a delay input is coupled to the data output and a delay output is coupled to the reset input. The delay module to delay the captured edge by a predetermined period and to generate a delay signal from the delay output after the predetermined period. The pulsed digital module is to generate a first clock edge of the sampling clock at the data output after the predetermined period. An apparatus, system, and method to embed a sampling clock signal via an encoded signal comprising n bits and to transmit the encoded signal to a single-wire as a serial bit sequence of n bits. The encoded signal represents a logic bit having an encoding clock period TCLK. Other embodiments are described and claimed.