Single-Wire Debug Port Over CAN for Pin-Limited SoC Access
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Solution Overview
Problem
Existing system-on-chip (SoC) debugging methods face challenges due to pin limitation constraints, requiring additional I/O pins for debug interfaces, which are undesirable and interfere with communication protocols, especially in automotive systems where connector pin limitations are stringent.
Innovation Solution
A single signal debug port (SSDP) protocol that encodes SWD signals using pulse-width modulation (PWM) over a Controller Area Network (CAN) Bus, allowing communication through a single wire, utilizing existing CAN transceivers and I/O pins without interfering with application-specific functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated pin is used to force the interface into debug interface configuration, then debug functionality is enabled, but additional I/O pins are required which increases system cost and is undesirable due to pin limitation constraints
Solution Approach 1:
The GPIO pins are designed to serve multiple functions: they can operate as general-purpose I/O pins for normal system operation, or be reconfigured as debug interface pins when needed. The debug host forces the GPIO pins into debug interface configuration by driving a control pin to a logic high state, allowing the same physical pins to fulfill both debug and general-purpose functions without requiring additional dedicated debug pins.
2Device complexity
If more than one communication interface is mapped onto the same set of GPIO pins, then pin utilization is improved, but the mapped communication protocol cannot be used when the debugger is connected
Solution Approach 1:
The system dynamically reconfigures the GPIO pins between different functional modes based on operational requirements. When debugging is needed, the debug host forces the pins into debug interface configuration. When debugging is not active, the pins return to their normal communication interface functions. This dynamic switching allows full utilization of the same physical pins for multiple protocols at different times without permanent conflict.
3Reliability
If additional I/O pins are allocated for debug interfaces, then debug capability is enhanced, but system cost increases and pin limitation constraints are violated
Solution Approach 1:
The invention reuses existing GPIO pins for debug interface functionality, eliminating the need for additional dedicated debug pins. By forcing the GPIO pins into debug interface configuration through control signal manipulation, the system achieves full debug capability using pins that would otherwise be used for general-purpose I/O or communication interfaces, thus maintaining pin limitation compliance while enhancing debug capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The SSDP protocol enables efficient debugging of SoCs by reducing overheads, maintaining system functionality, and supporting all debug features without additional hardware, while avoiding interference with existing communication protocols.
Implementation Method 1
The SSDP target circuit is configured to encode the SWD signals to SSDP signals for communication over a Controller Area Network (CAN) Bus between the circuit and the debugging tool. The SSDP signals are pulse-width modulation (PWM) encoded signals of the SWD signals.
Implementation Method 2
communicating the SSDP signals between the SSDP host circuit and the SSDP target circuit over a Controller Area Network (CAN) Bus
Data Source
AI summary
According to an embodiment, a system is provided that includes a debugging tool and an application board. The debugging tool includes a serial wire debug (SWD) host coupled to a single signal debug port (SSDP) host. The application board includes an SWD target coupled to an SSDP target. The SWD target is configured to communicate SWD signals with the SWD host. The SSDP target is configured to encode the SWD signals to SSDP signals for communication over a Controller Area Network (CAN) Bus between the application board and the debugging tool. The SSDP signals are pulse-width modulation (PWM) encoded signals of the SWD signals. An SWD clock signal generated by the SWD host is the carrier signal for the PWM encoded signals. The SSDP target is configured to decode the SSDP signals received from the SSDP host over the CAN Bus to the SWD signals.