Single-Wire Die-to-Die Interface With Three-Level Clock Recovery
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Solution Overview
Problem
Existing die-to-die interfaces are overly complex and require multiple lines and a precision time base, making it difficult and expensive to connect low-voltage semiconductor devices with high-voltage analog circuits.
Innovation Solution
A single-wire communication protocol using three voltage levels (high, mid, and low) to transmit data without a separate clock signal, utilizing comparators to determine bit states and derive timing information from voltage transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a dual die concept is implemented to separate high voltage and low voltage circuits, then voltage compatibility is improved, but interface complexity increases due to requiring multiple lines and precision time base
Solution Approach 1:
The patent merges multiple interface functions (data transmission, clock signaling, and voltage level indication) into a single wire communication channel. By encoding voltage level information and timing data together with data bits using three voltage levels (high, mid, low), the interface requires only one physical connection between dies, dramatically reducing complexity while maintaining voltage compatibility
Solution Approach 2:
The single wire interface serves multiple functions simultaneously: it transmits data bits, provides clock timing through transition edges, indicates voltage level information, and enables bidirectional communication. This multi-functional approach eliminates the need for separate dedicated lines for each function, resolving the contradiction between adaptability and complexity
2Reliability
If multiple lines and precision time base are used for die to die interface, then communication reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent extracts the clock signaling function from a separate dedicated clock line and embeds it within the data transmission wire itself. By using edge transitions of the three voltage levels to indicate timing information, the interface achieves reliable synchronized communication without requiring additional clock infrastructure, reducing manufacturing cost while maintaining reliability
Solution Approach 2:
The patent changes the voltage level parameters from traditional binary (high/low) to ternary (high/mid/low), enabling encoding of additional information including timing and control signals within the same transmission medium. This parameter expansion allows reliable communication with fewer physical lines, lowering manufacturing complexity and cost
3Device complexity
If three voltage levels are used to transmit bits on a single wire, then interface simplicity is improved, but signal detection complexity increases
Solution Approach 1:
The patent introduces comparator circuits as intermediary devices that automatically compare the received voltage level against reference thresholds and convert the three-level analog signal into clean digital logic levels. These comparators simplify the detection process by handling the complexity of three-level recognition, allowing the rest of the digital logic to operate with standard binary signals while maintaining interface simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Facilitates efficient, high-bandwidth communication between dual dies with easy clock recovery, allowing for seamless integration of high and low voltage circuits while reducing interface complexity and cost.
Implementation Method 1
comparators are used to indicate whether or not an input voltage level is less than a low voltage threshold (Vrl) and whether or not an input voltage is greater than a high voltage threshold (Vrh)
Data Source
AI summary
A receiver circuit receives an input voltage waveform from a single wire and generates an output bit stream. The receiver includes a voltage determination circuit which indicates whether a voltage level of the input voltage waveform has one of a high level that is higher than a high voltage threshold, a low level that is lower than a low voltage threshold, or a mid level that is between the high and low voltage levels. The receiver includes a bit value generator which provides a next bit value of the output bit stream as a first value when the voltage level is the high level, as a second value when the voltage level is the low level, and as a same value as an immediately previous bit value of the output bit stream when the voltage level is the mid level. The first and second values correspond to opposite logic states.