Single-Wire Bi-Directional Interface for High-Speed Data Transfer

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Solution Overview

Problem

As computing systems become more complex, the interconnect architecture to couple and communicate between components also increases in complexity, necessitating efficient energy conservation and energy efficiency while meeting bandwidth requirements, particularly in diverse market segments such as servers and mobile ecosystems.

Innovation Solution

The implementation of a single wire bi-directional interface capable of full-duplex operation at high data bit rates, enabling digital microphones to be connected using only two physical pins, and allowing two identical microphones to be attached to the same bus interface for noise cancellation, with a bus master device that generates wide and narrow clock pulses to transmit data to slave devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single wire bi-directional interface is implemented, then the number of physical pins is reduced and power consumption is lowered, but achieving full-duplex operation at high data bit rates becomes more challenging

Engineering Contradiction:
Improvenumber of physical pinsVSAvoiddata transfer rate
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent merges transmit and receive functions into a single physical wire interface. The bi-directional interface allows full-duplex operation by combining multiple communication functions (data transmit, data receive, clock signaling) onto a single physical connection between master and slave devices, thereby reducing pin count while maintaining high data transfer rates

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent utilizes voltage level transitions and timing dimensions to encode multiple signals on a single wire. By varying voltage levels and timing sequences, the interface can simultaneously or alternately transmit multiple types of information (data bits, clock signals, control information) through the same physical medium, effectively adding informational dimensions to compensate for the reduced physical dimension

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If multiple identical microphones are connected to the same bus interface, then noise cancellation is enabled, but the complexity of managing multiple slave devices increases

Engineering Contradiction:
Improvenoise cancellation capabilityVSAvoidbus interface management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The bus interface is designed with universal addressing and control mechanisms that can accommodate any number of slave devices. Each microphone (slave device) is assigned a unique address, and the master device can selectively communicate with any slave by addressing it specifically. This universal design allows multiple identical microphones to be connected without increasing the fundamental interface complexity, as the same bus protocol and control logic handle all devices

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The bi-directional interface enables feedback mechanisms where slave devices can send status information, error signals, and data back to the master device through the same single wire. This feedback capability allows the master to manage multiple slaves efficiently by receiving acknowledgment and status information, coordinating their operation for noise cancellation without requiring separate control lines for each device

Inventive Principle:
Principle #23Feedback

Data Source

PatentEP2778937B1Method, apparatus, and system for improving inter-chip and single-wire communication for a serial interface
Publication Date: 2017.10.04 INTEL CORP
  • EP2778937B1 patent drawingFigure 1
  • EP2778937B1 patent drawingFigure 2
  • EP2778937B1 patent drawingFigure 3

AI summary

A system and method consistent with the present disclosure includes a master device, bus interface link, and slave device. The master device includes a power supply and a detection unit to detect an impedance of the power supply. The inverter provides a first path to the power supply on a first stage of a clock signal and. Further, the inverter provides a second path to a first ground line on a second stage of a clock signal. The bus interface link couples the master device to a slave device. Additionally, a bi-directional communications line is coupled to the bus interface link. A gating component provides a second ground line to the power supply through the first path. Furthermore, a receiver determines bit values from a plurality of clock data signals transmitted from the master device.