Single Wire Interface for ICs Reducing Pin Count and Power
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Solution Overview
Problem
Existing serial communication systems for ICs, such as SPI and I2C, require multiple pins and consume significant power due to the need for separate clock lines, which increases costs and power consumption.
Innovation Solution
A master device and slave device communicate using a single wire interface, where the master device generates an oversampling clock signal to synchronize data transmission, eliminating the need for a separate clock line and reducing the number of pads required, thereby decreasing the size and power consumption of the ICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate clock line is used for synchronization in serial communication (I2C), then data transmission synchronization is achieved, but power consumption increases and the number of pins increases
Solution Approach 1:
The patent combines the clock signal and data signal into a single wire interface. The transmitting device embeds clock information within the data transmission stream, allowing the receiving device to extract synchronization timing from the data itself rather than requiring a separate clock line. This merging eliminates the dedicated clock wire while maintaining synchronization capability.
Solution Approach 2:
The single wire interface serves multiple functions simultaneously: it transmits both data and clock synchronization signals, replaces the need for separate SDA and SCL lines in I2C, and provides bidirectional communication capability. This multi-functionality reduces the pin count while maintaining full communication functionality.
2Reliability
If multiple pins are used for serial communication (SPI uses 3-4 pins), then reliable data transmission is achieved, but the number of pins increases leading to higher IC costs
Solution Approach 1:
The patent merges multiple communication functions (data transmission, clock synchronization, and control signals) into a single wire interface. By encoding timing and control information within the data stream itself, the system eliminates the need for separate pins for clock, data, and control functions that would otherwise be required in traditional SPI or I2C implementations.
Solution Approach 2:
The patent transitions from a multi-dimensional pin interface (separate physical lines for clock, data, and control) to a single-dimensional wire interface by encoding multiple functions within the temporal structure of a single signal stream. This dimensional consolidation reduces physical complexity while maintaining functional reliability.
3Device complexity
If a single wire interface is used without a separate clock line, then the number of pins is reduced and power consumption decreases, but synchronization of data transmission becomes more challenging
Solution Approach 1:
The patent implements feedback mechanisms where the receiving device monitors the incoming data stream to detect timing patterns and adjusts its sampling clock accordingly. This feedback loop allows the receiver to automatically synchronize with the transmitter's data rate and timing without requiring a separate clock line, maintaining synchronization reliability through adaptive timing adjustment.
Solution Approach 2:
The patent incorporates preliminary synchronization sequences or timing markers within the data stream that allow the receiving device to establish synchronization before actual data transmission begins. These pre-encoded timing references enable the receiver to lock onto the correct sampling phase in advance, ensuring reliable data capture throughout the communication session.
Data Source
AI summary
A data processing system includes a master device and a slave device. The master device includes a first single pad, a first control circuit, a first frame generator configured, and a first processing circuit. The slave device includes a second single pad, a second control circuit, a second frame generator, and a second processing circuit. A clock source is configured to provide a clock signal to the master device and the slave device. The master device communicates with the slave device through a single wire, the single wire being connected between the first single pad and the second single pad, wherein the single wire is bidirectional. A first frame is transmitted from the master device to the slave device, and a second frame is transmitted from the slave device to the master device.