Single-Wire Interface for IC Configuration via Superimposed Signal
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Solution Overview
Problem
Existing communication protocols between integrated circuits often require multiple lines and additional clock or synchronization lines, which can be costly and complex, especially for configuring devices without non-volatile memory that need initial configuration data.
Innovation Solution
A single-wire interface method where a transmitter sends logical information superimposed on a clock signal from the receiver, allowing both devices to access the bus without additional lines, with the receiver determining the information by interpreting signal levels, and the transmission rate can fluctuate without requiring synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple lines and additional clock or synchronization lines are used for communication between integrated circuits, then communication reliability and synchronization are improved, but device complexity and cost increase
Solution Approach 1:
The patent combines the data transmission function and clock signal function into a single physical line. The receiver generates a clock signal that is transmitted to the transmitter, which modulates its data signal onto the clock signal's recessive phases. This merging eliminates the need for separate clock lines and synchronization circuits, reducing device complexity while maintaining communication reliability through the self-synchronizing nature of the protocol
Solution Approach 2:
The single communication line serves multiple functions simultaneously: it carries the clock signal from the receiver, transmits data from the transmitter through modulation, and provides bidirectional communication capability. The clock line also serves as the data transmission medium, and the same line enables both synchronization and information transfer, demonstrating multi-functionality that reduces overall system complexity
2Device complexity
If a single line is used for communication between integrated circuits, then device complexity and cost are reduced, but communication reliability and synchronization capability deteriorate
Solution Approach 1:
The receiver generates a periodic clock signal that is transmitted to the transmitter. This periodic action creates regular time intervals (recessive and dominant phases) that structure the communication protocol. The periodic clock signal enables the transmitter to know when to place data bits on the line and allows the receiver to sample data at precise moments, maintaining communication reliability without requiring separate synchronization lines
Solution Approach 2:
The protocol implements a feedback mechanism where the receiver's clock signal serves as the timing reference for the entire communication. The transmitter monitors the clock signal phases and adjusts its data transmission accordingly, placing bits during recessive phases. This feedback loop ensures that both devices remain synchronized automatically, maintaining communication reliability while using only a single line
3Measurement precision
If clock synchronization is required for communication, then data transmission accuracy is improved, but setup complexity and configuration effort increase
Solution Approach 1:
The communication system is self-synchronizing because the receiver generates the clock signal that both devices use for timing. The transmitter automatically detects the clock signal phases and places data bits during the appropriate recessive phases without external synchronization. The system serves its own synchronization needs internally, eliminating the need for external clock distribution or manual synchronization configuration, thus improving ease of operation while maintaining data transmission accuracy
4Device complexity
If fixed transmission rate is used, then synchronization is simplified, but adaptability to different devices and conditions is reduced
Solution Approach 1:
The transmission rate in this protocol is dynamic rather than fixed. The receiver can adjust its clock signal frequency based on the capabilities and requirements of the transmitter, allowing the system to adapt to different devices and communication conditions. The protocol maintains synchronization through the periodic clock signal structure while allowing the actual transmission rate to vary, achieving both simplicity and adaptability
Data Source
Figure 1~2
AI summary
The invention relates to a method for transmitting logic information from a transmitter to a receiver via a single line, wherein the receiver is connected to the transmitted by means of the line, wherein the receiver applies a first signal to the line and the first signal consists of alternating recessive and dominant levels, wherein the transmitter applies a second signal to the line and the second signal from the transmitter is superimposed on the line at least in the sections in which the first signal has a recessive level, wherein the second signal consists of a sequence of recessive and dominant levels, and wherein the receiver determines the logic information to be received from the second signal.