Single-Wire Serial Synchronization for Cascaded Slave Timing
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Solution Overview
Problem
In single-wire serial communication systems, the asynchronous nature of input signals with internal clocks of slaves leads to signal delays and variations, resulting in transmission errors after multiple stages of cascading.
Innovation Solution
A synchronous transmission method is introduced, where the output signal of each slave is controlled in a serial communication system. During a synchronous control interval, the output signal is synchronized with the input signal, and during a data control interval, the output signal is controlled by a first signal to maintain synchronization, with the start moment of the first signal period delayed compared to the input signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the internal clock of each slave is used for reply and synchronization in single-wire serial communication, then the communication system can operate with simple structure and low power consumption, but signal delays and duty cycle variations occur leading to transmission errors
Solution Approach 1:
The patent introduces periodic control intervals (synchronous control intervals and data control intervals) to periodically adjust and maintain the output signal waveform. This periodic action ensures that despite asynchronous input, the output signal maintains proper synchronization and duty cycle, eliminating transmission errors while keeping the system relatively simple.
Solution Approach 2:
The patent changes the control parameters by introducing specific control intervals with defined timing relationships. The synchronous control interval aligns the output signal period with the input signal period, while the data control interval handles data transmission. This parameter-based control approach maintains reliability without requiring complex hardware modifications.
2Adaptability or versatility
If asynchronous control is used in multi-stage cascading serial communication, then the system can operate independently at each stage, but signal levels and duty cycles change leading to transmission errors
Solution Approach 1:
The patent implements a feedback mechanism where the output signal of each slave is monitored and adjusted based on control intervals. The synchronous control interval specifically feeds back timing information to realign the output signal period with the input signal period, ensuring signal integrity is maintained across multiple cascading stages while preserving independent operation capability.
3Reliability
If higher internal clock frequency is used to reduce signal delays and synchronization issues, then transmission reliability improves, but digital power consumption and chip area increase
Solution Approach 1:
The patent performs preliminary synchronization actions during the synchronous control interval before data transmission begins. By pre-aligning the output signal period with the input signal period and establishing proper timing relationships in advance, the system achieves reliable synchronization without requiring continuously high clock frequencies, thus reducing power consumption while maintaining accuracy.
Data Source
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AI summary
A synchronous transmission method, and a chip and a serial communication system applying the same are provided. Synchronous control intervals and data control intervals are alternately arranged based on a time sequence, ensuring that during the synchronous control intervals, the periods of the input and output signals are synchronized, and during the data control intervals, the data that the slaves need to output is generated. The start moment of the period of the output signal is controlled by the input signal, while the data of the output signal is controlled by the first signal. Additionally, the synchronous transmission method of the present disclosure uses a lower internal clock frequency within the chip, reducing digital power consumption and chip area, which in turn lowers the chip cost.