Single-XOR CRC Circuit Using Message Padding for Wide Data Words
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current cyclic-redundancy-check-code-computation circuits require a large number of transistors and components due to increasing data word lengths, leading to increased costs and slower computation speeds as bandwidths rise in electronic communications.
Innovation Solution
The implementation of a component-efficient CRC-code-computation logic using a single XOR matrix with message-padding logic, which transforms uneven message lengths into evenly divisible lengths by prepending padding bytes, reducing the need for multiple XOR matrices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of XOR matrices is increased to handle larger data word lengths, then the CRC code computation accuracy is improved, but the number of circuit components increases
Solution Approach 1:
The patent divides the message into multiple blocks, each block being processed by a single XOR matrix. The message is segmented such that each segment can be handled by one XOR matrix instance, allowing parallel processing while maintaining accuracy for large data word lengths without requiring a proportional increase in the number of XOR matrices.
Solution Approach 2:
The patent introduces a new dimension of processing by implementing a hierarchical block structure where messages are divided into blocks that are further divided into segments. This multi-level segmentation allows the system to handle arbitrarily large data word lengths using a fixed number of XOR matrices by processing data in organized blocks rather than requiring one matrix per data element.
2Productivity
If the number of XOR matrices is increased to handle larger data word lengths, then the computation capability is improved, but the manufacturing cost increases
Solution Approach 1:
The patent makes a single XOR matrix universal by designing it to process multiple blocks of data through segmented processing. The same XOR matrix instance can be reused across different blocks and segments, eliminating the need for multiple dedicated XOR matrices for each data element. This multi-functional approach maintains high computation capability while significantly reducing the total number of circuit components required.
Solution Approach 2:
The patent implements a block-based processing scheme where the XOR matrix processes one block at a time, then its state is recovered and reused for the next block. This allows the same hardware resources to be discarded (finished processing one block) and recovered (reused for the next block), maximizing resource utilization and reducing the need for redundant components.
3Speed
If the number of XOR matrices is increased to handle larger data word lengths, then the processing speed is improved, but the computation time increases
Solution Approach 1:
The patent segments the message into blocks that can be processed in parallel or in an optimized sequence. By dividing the data into manageable segments, the system can initiate processing of multiple blocks simultaneously or overlap processing stages, maintaining high processing speed while avoiding the sequential bottlenecks that would increase total computation time.
Solution Approach 2:
The patent ensures continuous useful action by implementing a pipeline where while one block is being processed, preparation for the next block can begin, and results from completed blocks can be finalized. This continuous processing approach eliminates idle time between operations and maintains high processing speed without extending the overall computation time proportionally to the data size.
Data Source
AI summary
With CRC-code-computation logic used in electronic-communications hardware, many current implementations employ a number n of XOR matrices equal to the number of bytes in the fundamental data unit, or word, operated on by the CRC-code-computation logic. As the size, in bytes, of the fundamental-data-unit increases, due to increases in the widths of internal data-transmission components, the number n of XOR matrices in CRC-code-computation logic has correspondingly increased. A component-efficient CRC-code-computation logic employs message-padding logic in order to compute CRC codes using only a single XOR matrix. The message-padding logic takes advantage of certain characteristics of CRC codes to transform original input messages having lengths, in bytes, that are not evenly divisible by the length of the fundamental data unit into messages that are evenly divisible by the length of the fundamental data unit by prepending padding bytes to the original messages.