DisplayPort Sink Clock Recovery Using Buffer Water-Level Feedback
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Solution Overview
Problem
The DisplayPort interface experiences frequency drift in the pixel clock signal, leading to deviations in the recovered image format, causing abnormal operations in back-end circuits due to environmental factors and electromagnetic interference, despite frequency spreading designs.
Innovation Solution
A sink device with a buffering unit and a clock generating unit that adjusts the pixel clock signal rate based on a water level value generated from monitoring the decoding data flow, ensuring synchronization with the symbol clock signal to stabilize the pixel clock rate and correct frequency drift.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If frequency spreading design is used to reduce electromagnetic interference, then anti-interference capability is improved, but frequency drift occurs causing image format deviation
Solution Approach 1:
The patent implements a feedback mechanism by monitoring the water level in the buffering unit and using this information to dynamically adjust the pixel clock signal frequency. The buffering unit's fill level serves as feedback about the frequency drift state, and the controller adjusts the clock frequency accordingly to maintain accurate image format recovery while preserving the frequency spreading anti-interference benefit.
Solution Approach 2:
The patent dynamically changes the pixel clock signal frequency parameter based on the buffering unit's water level state. By adjusting the clock frequency in response to detected drift conditions, the system corrects image format deviations without eliminating the frequency spreading design that provides electromagnetic interference resistance.
2Measurement precision
If pixel clock signal frequency is adjusted to correct drift, then image format accuracy is improved, but clock signal stability becomes more difficult to maintain
Solution Approach 1:
The patent introduces dynamic adjustment of the pixel clock signal frequency based on real-time monitoring of the buffering unit's water level. Rather than using a fixed frequency, the system adaptively modifies the clock frequency to compensate for drift while maintaining overall stability through controlled, incremental adjustments rather than abrupt changes.
Solution Approach 2:
The system performs self-correction by automatically detecting frequency drift through the buffering unit's water level monitoring and autonomously adjusting the pixel clock frequency without external intervention. This self-regulating mechanism maintains image format accuracy while preserving clock signal stability through balanced adjustment strategies.
3Measurement precision
If buffering unit water level is monitored to detect frequency drift, then drift detection accuracy is improved, but device complexity increases
Solution Approach 1:
The patent uses the buffering unit's water level as an intermediary indicator of frequency drift. Rather than directly measuring complex clock signal frequency deviations, the system monitors the simpler water level state in the buffer, which indirectly reflects drift conditions. This intermediary measurement approach improves detection accuracy while avoiding the need for complex direct frequency measurement circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively stabilizes the pixel clock rate, ensuring the recovered image format matches the original format transmitted by the source device, preventing abnormal operations in back-end circuits and reducing the impact of environmental factors and electromagnetic interference.
Implementation Method 1
a phase-locked loop which comprises a phase frequency detector, a low pass filter, and a voltage-controlled oscillator
Data Source
AI summary
The invention discloses a sink device. The sink device comprises a buffering unit and a clock generating unit. The buffering unit receives a decoding data according to a symbol clock signal, reads the decoding data according to a pixel clock signal, and generates a water level value. The clock generating unit receives the symbol clock signal to generate the pixel clock signal and adjusts a rate of the pixel clock signal according to the water level value and/or a phase difference signal.