Low Resistance Sinker Contact for High Power Transistors
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Solution Overview
Problem
High power transistors in semiconductor devices face significant voltage drops due to high contact resistance, limiting their performance, and increasing the diffusion area or forming multiple contacts to reduce resistance often increases the chip area and diffusion capacitance, compromising circuit performance.
Innovation Solution
A semiconductor device with low resistance sinker contacts is achieved by etching through a lightly doped layer into a more heavily doped layer and filling the contact with a metallic material, such as CVD-W or electroplated copper, which significantly reduces contact resistance by increasing the contact area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the diffusion area is increased to reduce contact resistance, then contact resistance decreases, but chip area increases
Solution Approach 1:
The patent transitions from a two-dimensional surface contact to a three-dimensional vertical contact structure. The sinker contact extends vertically through the lightly doped layer into the heavily doped layer, utilizing the depth dimension to increase contact area without expanding the horizontal chip footprint. This vertical penetration provides low resistance contact while maintaining minimal surface area occupation.
Solution Approach 2:
The sinker contact structure embeds the metallic material within an etched opening that penetrates through the lightly doped layer into the heavily doped layer. This nested configuration allows the contact structure to be contained within the vertical profile of the device, integrating the low resistance path without adding lateral space requirements.
2Reliability
If multiple contacts are formed to reduce resistance, then contact resistance decreases, but diffusion capacitance increases
Solution Approach 1:
Instead of forming multiple lateral contacts that would increase diffusion area and associated capacitance, the patent creates a single vertical sinker contact that extends into the heavily doped layer. This vertical approach provides multiple parallel conduction paths through the depth of the structure without increasing the horizontal diffusion area, thereby reducing contact resistance while minimizing diffusion capacitance.
3Reliability
If a heavily doped diffusion column is formed to reduce contact resistance, then contact resistance decreases, but voltage drop increases under high current
Solution Approach 1:
The patent pre-forms a heavily doped layer at the target location before creating the sinker contact opening. This preliminary doping action ensures that when the metallic material is deposited, it immediately contacts the heavily doped region, establishing a low resistance path that can handle high current with minimal voltage drop. The heavy doping is prepared in advance to optimize the electrical properties before the final contact formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistance, enhancing the performance of high power transistors by allowing higher current flow with lower voltage drops, while also minimizing the area and capacitance of the integrated circuit.
Implementation Method 1
the low resistance sinker contact is filled with a metallic material
Implementation Method 2
a sinker contact is formed by implanting dopant at a series of different energies to form a highly doped diffusion column
Implementation Method 3
the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer
Data Source
AI summary
An semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material. A method for forming a semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material.