SiN Protective Layer for Dummy Gate CMP in Metal Gate Fabrication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The conventional two-step CMP process for manufacturing semiconductor devices faces challenges in filling gate materials due to increased difficulty caused by having to account for dummy gate losses, leading to deeper cavities and reduced accuracy in gate formation.
Innovation Solution
A method is introduced where a SiN layer is formed over the NMOS region before performing gate material filling and CMP in the PMOS region, reducing dummy gate loss and improving the filling process by controlling the CMP to stop at the SiN layer, thus reducing the initial height of the dummy gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional two-step CMP process is used for manufacturing semiconductor devices, then the gate electrode can be formed, but the dummy gate loss increases leading to deeper cavities and reduced accuracy in gate formation
Solution Approach 1:
The patent applies preliminary action by forming a protective layer over the dummy gate before the CMP process. This protective layer prevents dummy gate material loss during CMP, eliminating the need for compensating for dummy gate losses in subsequent processing steps. The protective layer is formed in advance to protect the dummy gate during the upcoming CMP operation.
Solution Approach 2:
The patent introduces an intermediary protective layer between the dummy gate and the CMP process. This intermediary layer acts as a barrier that prevents direct contact between the CMP slurry and the dummy gate material, thereby preventing dummy gate loss while still allowing the CMP process to proceed for planarizing the gate electrode.
2Productivity
If the CMP process is performed without accounting for dummy gate losses, then the processing speed increases, but the cavity depth increases and filling accuracy decreases
Solution Approach 1:
The protective layer is formed in advance before the CMP process to prevent dummy gate loss. This preliminary protective measure eliminates the need for complex compensation calculations and multiple processing steps, thereby maintaining high processing speed while ensuring accurate gate filling.
Solution Approach 2:
The patent implements a feedback mechanism where the protective layer thickness is controlled to compensate for the expected dummy gate loss. By monitoring and controlling the protective layer formation, the process ensures that the dummy gate maintains its original dimensions, providing feedback control for accurate gate filling.
3Ease of manufacture
If the dummy gate height is reduced, then the filling process is improved, but the dummy gate becomes more susceptible to loss during CMP
Solution Approach 1:
The protective layer serves as an intermediary that allows the dummy gate to maintain an optimal height for easy filling while protecting it from CMP-induced loss. The protective layer compensates for the reduced dummy gate height by providing additional material that prevents loss during CMP processing.
Solution Approach 2:
The protective layer provides beforehand cushioning by being formed in advance to protect the dummy gate during CMP. This cushioning effect ensures that even if the dummy gate height is reduced for easier filling, the protective layer prevents any material loss during the subsequent CMP process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces dummy gate loss and enhances the filling process of gate materials, improving the accuracy and efficiency of metal gate formation in semiconductor devices.
Implementation Method 1
forming a SiN layer over the NMOS region
Implementation Method 2
performing a CMP to polish a top surface of PMOS
Data Source
AI summary
One aspect of the present disclosure is a method of fabricating metal gate by forming a silicon-nitride layer (SiN) over a dummy gate at a second metal gate type transistor region (e.g. NMOS) avoid dummy gate loss during a CMP process for a PMOS gate. The method can comprise after performing a patterning process to remove hard masks at PMOS and NMOS regions, forming a SiN layer over the NMOS region; performing a patterning process to open the PMOS region and filling gate materials in the PMOS region; performing a CMP to polish a top surface of PMOS such that the polishing stops at SiN. In this way, dummy gate loss can be reduced during the first aluminum CMP step and thus can reduce initial height of dummy gate as compared to the convention method, and improve the filling process of the dummy gate as compared to the conventional method.