Semiconductor Chip Sinter-Bonding Material Transfer
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Solution Overview
Problem
The existing semiconductor device manufacturing process using sinter-bonding material results in significant loss due to the large clearance between chips during the lamination and transfer process, leading to inefficient supply and bonding.
Innovation Solution
A method involving dicing, lamination, picking-up, temporary securing, and sinter bonding steps, where a sinter-bonding sheet with conductive metal-containing sinterable particles is applied to a diced semiconductor wafer with reduced chip spacing, allowing for efficient transfer and bonding of the sinter-bonding material to each chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a Cu interlayer is formed in a semiconductor device, then electrical conductivity is improved, but diffusion barriers are reduced leading to device reliability degradation
Solution Approach 1:
The patent divides the interlayer structure into multiple segments: a Cu interlayer for electrical conductivity, and separate diffusion barrier layers (first and second diffusion barriers) to prevent diffusion. This segmentation allows each layer to perform its specific function without interfering with others, resolving the contradiction between conductivity improvement and diffusion barrier maintenance.
Solution Approach 2:
The patent introduces intermediary diffusion barrier layers between the Cu interlayer and surrounding materials. These barrier layers act as mediators that prevent direct contact and diffusion between Cu and adjacent layers, while allowing the Cu interlayer to maintain its electrical conductivity function. The first diffusion barrier is positioned between the Cu interlayer and the first conductor pattern, and the second diffusion barrier is positioned between the Cu interlayer and the second conductor pattern.
2Reliability
If Cu is used as interlayer material, then electrical conductivity is enhanced, but manufacturing complexity increases due to diffusion control requirements
Solution Approach 1:
The interlayer structure is segmented into distinct functional layers: Cu interlayer for conductivity, first diffusion barrier for preventing diffusion toward the first conductor pattern, and second diffusion barrier for preventing diffusion toward the second conductor pattern. This segmentation simplifies the manufacturing process by assigning specific functions to each layer, making the overall complex structure manageable through modular design.
3Reliability
If Cu interlayer is formed to improve conductivity, then electrical performance is enhanced, but metal migration and void formation occur reducing reliability
Solution Approach 1:
The patent introduces diffusion barrier layers as intermediary substances between the Cu interlayer and adjacent conductor patterns. These barrier layers prevent direct interaction that would lead to metal migration and void formation, while allowing the Cu interlayer to maintain its electrical performance. The first diffusion barrier prevents Cu migration toward the first conductor pattern, and the second diffusion barrier prevents Cu migration toward the second conductor pattern.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces material loss and ensures reliable bonding by efficiently supplying the sinter-bonding material to each semiconductor chip, enhancing the bonding process and reducing production costs.
Implementation Method 1
a first diffusion barrier between the Cu interlayer and the first conductor pattern
Implementation Method 2
a second diffusion barrier between the Cu interlayer and the second conductor pattern
Data Source
Figure 1(a)~1(d)
Figure 2~3(b)
Figure 4(a)~4(b)
AI summary
A manufacturing method includes the step of forming a diced semiconductor wafer (10) including semiconductor chips (11) from a semiconductor wafer (W) typically on a dicing tape (T1). The diced semiconductor wafer (10) on the dicing tape (T1) is laminated with a sinter-bonding sheet (20). The semiconductor chips (11) each with a sinter-bonding material layer (21) derived from the sinter-bonding sheet (20) are picked up typically from the dicing tape (T1). The semiconductor chips (11) each with the sinter-bonding material layer are temporarily secured through the sinter-bonding material layer (21) to a substrate. Through a heating process, sintered layers are formed from the sinter-bonding material layers (21) lying between the temporarily secured semiconductor chips (11) and the substrate, to bond the semiconductor chips (11) to the substrate. The semiconductor device manufacturing method is suitable for efficiently supplying a sinter-bonding material to individual semiconductor chips while reducing loss of the sinter-bonding material.