Sinter Paste Flattening for High-Density Power Chip Bonding

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Solution Overview

Problem

The sinter-bonding technique for semiconductor devices often results in surface projections on the sinter paste, leading to uneven pressure on power semiconductor chips and potential damage, as well as reduced packaging density due to the need for extra printing area to avoid these projections.

Innovation Solution

A semiconductor device with a bonding layer featuring varying porosity between its middle and end parts, achieved by flattening the sinter paste surface before chip deposition through pressure application, allowing for stable bonding and high-density packaging.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If sinter paste is applied to bond the semiconductor chip, then high heat resistance and reliability are achieved, but surface projections are formed causing uneven pressure and potential chip damage

Engineering Contradiction:
Improvebonding reliabilityVSAvoidsurface projections causing uneven pressure
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies a preliminary pressure treatment to the sinter paste before depositing the semiconductor chip. This preliminary action flattens the surface projections of the sinter paste, creating a uniform bonding surface that prevents uneven pressure distribution and potential chip damage during the bonding process, while maintaining the high heat resistance and reliability benefits of sinter bonding

Inventive Principle:
Principle #10Preliminary action

2Reliability

If extra printing area is provided to avoid projections on sinter paste, then chip damage is prevented, but packaging density is reduced

Engineering Contradiction:
Improvechip bonding reliabilityVSAvoidpackaging density
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By applying preliminary pressure to flatten the sinter paste surface before chip deposition, the patent eliminates the need for extra printing area that would be required to avoid surface projections. This preliminary flattening action allows the chip to be bonded directly over the entire sinter paste area, maximizing packaging density while ensuring uniform pressure distribution and bonding reliability

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If sinter paste surface is flattened by pressure application, then uniform stress distribution is achieved, but additional process step is required

Engineering Contradiction:
Improvestress distribution uniformityVSAvoidnumber of process steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent combines the preliminary pressure treatment step with the existing sinter paste application and drying process. By integrating the flattening action into the established manufacturing workflow rather than adding it as a completely separate operation, the patent achieves uniform stress distribution while minimizing the increase in process complexity

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method ensures even stress distribution and prevents chip damage, enabling high-density packaging with high heat resistance and reliability by forming a uniform and stable bonding layer.

Implementation Method 1

heating and pressure-application treatment before sintering the sinter paste

Methodology Applied
Scientific EffectSintering: Sintering

Data Source

PatentUS20230369276A1Semiconductor device and method of manufacturing the same
Publication Date: 2023.11.16 FUJI ELECTRIC CO LTD
  • US20230369276A1 patent drawing
  • US20230369276A1 patent drawing
  • US20230369276A1 patent drawing

AI summary

Provided is a method of manufacturing a semiconductor device that can lead a surface of sinter paste to be flattened before depositing a power semiconductor chip so as to achieve high-density packaging. The manufacturing method applies sinter paste having a surface provided with a projection to a main surface of a conductive plate, dries the sinter paste, flattens the surface of the sinter paste by applying a pressure to the sinter paste so as to squash the projection on the surface of the sinter paste, deposits a semiconductor chip on the main surface of the conductive plate with the sinter paste interposed, and sinters the sinter paste by heating and pressure application to form a bonding layer so as to bond the conductive plate and the semiconductor chip together via the bonding layer.