Compound Semiconductor Substrate Using Sintered Body Seed Layer
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Solution Overview
Problem
Existing methods for manufacturing compound semiconductor substrates face challenges such as warpage, high costs, and limited design freedom due to the use of single crystal substrates, particularly sapphire or SiC substrates, which are expensive and difficult to process into larger diameters or thicker layers, and the difficulty in forming highly crystalline semiconductor layers on polycrystalline surfaces.
Innovation Solution
A compound semiconductor substrate is created using a sintered body as the ground substrate with a single crystal seed layer, where a buffer and active layer are sequentially crystal-grown, and the thermal expansion coefficient of the sintered body is matched to the semiconductor layer to suppress warpage and enhance breakdown voltage characteristics, while maintaining low resistance values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single crystal substrate (sapphire or SiC) is used as the ground substrate, then the crystallinity and quality of the compound semiconductor layer are improved, but the cost increases and the diameter is limited
Solution Approach 1:
The substrate is divided into two functional parts: a polycrystalline sintered body providing mechanical support and thermal management, and a single crystal seed layer providing crystalline template for epitaxial growth. This segmentation allows each part to optimize its own properties without the constraints of a complete single crystal substrate.
Solution Approach 2:
A single crystal seed layer acts as an intermediary between the polycrystalline sintered body and the compound semiconductor layer. The seed layer transfers the crystalline structure from the polycrystalline substrate to the epitaxial layer, enabling high-quality semiconductor growth on a cost-effective polycrystalline foundation.
2Area of stationary object
If a single crystal substrate with larger diameter is used, then the area for device fabrication is increased, but warpage occurs due to stress
Solution Approach 1:
The thermal expansion coefficient of the sintered body is specifically controlled to be 0.7 to 1.4 times that of the compound semiconductor layer. This parameter optimization minimizes thermal stress during heating and cooling cycles, preventing warpage even in large-diameter substrates.
3Ease of manufacture
If a polycrystalline surface is used as the ground substrate, then the cost is reduced and diameter can be increased, but the crystallinity of the formed semiconductor layer deteriorates
Solution Approach 1:
A single crystal seed layer is formed in advance on the polycrystalline sintered body before growing the compound semiconductor layer. This preliminary single crystal layer provides a perfect crystalline template that guides the epitaxial growth, ensuring high crystallinity in the final semiconductor layer despite the polycrystalline foundation.
4Adaptability or versatility
If the thermal expansion coefficient mismatch between sintered body and semiconductor layer is large, then the manufacturing flexibility is improved, but warpage and cracks increase
Solution Approach 1:
The thermal expansion coefficient of the sintered body is optimized to be within 0.7 to 1.4 times that of the compound semiconductor layer. This parameter control allows sufficient flexibility in material selection while maintaining stress compatibility to prevent warpage and cracking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in a substrate with superior properties, including reduced warpage and cracks, improved breakdown voltage, and low resistance values, making it suitable for large-size semiconductor devices with enhanced electrical properties.
Implementation Method 1
a thermal expansion coefficient of the sintered body is 0.7 times or more and 1.4 times or less an average thermal expansion coefficient of the entire compound semiconductor layer
Implementation Method 2
the compound semiconductor layer has a structure in which a buffer layer and an active layer are sequentially crystal-grown on the seed layer
Data Source
AI summary
A compound semiconductor substrate according to the present invention includes a compound semiconductor layer formed on one main surface of a ground substrate via a seed layer, wherein the ground substrate is formed of a sintered body, the seed layer is formed of a single crystal, the compound semiconductor layer includes a structure having a buffer layer and an active layer that are sequentially crystal-grown on the seed layer, a thermal expansion coefficient of the sintered body is 0.7 times or more and 1.4 times or less an average thermal expansion coefficient of the entire compound semiconductor layer, and an FWHM of an X-ray diffraction peak of the buffer layer obtained by an X-ray diffraction rocking curve measurement is 800 arcsec or less.