Porous Sintered Bonding Layer Layout for Predictable Chip Lifespan
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Solution Overview
Problem
Conventional semiconductor modules using solder-based bonding layers have a short but stable lifespan, while those using sintered material bonding layers have longer lifespans but exhibit variations in lifespan due to sudden damage from other deteriorating components.
Innovation Solution
A semiconductor device configuration featuring a bonding layer made from porous sintered material with the outer edge of the bonding interface between the conductive plate and the semiconductor chip positioned inside the semiconductor chip's circumference, creating stress-concentrated areas that intentionally cause cracks, thereby controlling the lifespan and avoiding lifespan variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bonding layer made from solder is used, then the lifespan is stable, but the lifespan is short due to deterioration of the bonding layer
Solution Approach 1:
The patent changes the material parameter of the bonding layer from solder to porous sintered material, which fundamentally alters the deterioration mechanism. The porous sintered material maintains stable bonding characteristics while resisting the thermal deterioration that limits solder-based bonding layers, thereby extending lifespan while preserving stability.
Solution Approach 2:
The patent employs a composite structure consisting of porous sintered material with specific pore characteristics. This composite material combines the benefits of strong bonding capability with enhanced thermal resistance and controlled deterioration behavior, resolving the contradiction between lifespan stability and lifespan extension.
2Duration of action of stationary object
If a bonding layer made from sintered material is used, then the lifespan is longer, but the lifespan varies due to sudden damage from other deteriorating components
Solution Approach 1:
The patent designs the porous sintered material with predetermined pore size distribution and bonding characteristics that control the timing and manner of deterioration. The material is engineered to deteriorate in a predictable, gradual manner rather than suddenly, allowing the lifespan to be both extended and made predictable through pre-planned material degradation behavior.
Solution Approach 2:
The patent utilizes porous sintered material with specifically controlled pore sizes and distributions. The porous structure provides controlled stress distribution and predictable deterioration patterns, preventing sudden catastrophic failures while maintaining extended lifespan. The pore structure acts as a stress buffer that prevents abrupt bond failures.
3Duration of action of stationary object
If the outer edge of the bonding interface is positioned inside the semiconductor chip circumference, then stress-concentrated areas are created that control lifespan, but this creates a specific structural configuration
Solution Approach 1:
The patent applies local quality by creating stress-concentrated areas at specific locations (the outer edge of the bonding interface inside the chip circumference) while maintaining uniform bonding properties in other regions. This localized stress concentration control allows predictable lifespan management without requiring complex overall structural changes, simplifying the device configuration while achieving lifespan control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures a controlled and predictable lifespan for semiconductor devices by intentionally causing cracks in the bonding layer, reducing the risk of sudden failure and lifespan variations compared to modules using sintered material bonding layers, and providing a longer lifespan compared to solder-based modules.
Implementation Method 1
a bonding layer including porous sintered material and arranged between the conductive plate and the semiconductor chip
Data Source
AI summary
Provided is a semiconductor device including a bonding layer made from sintered material and having a configuration capable of avoiding a variation in life span. The semiconductor device includes a conductive plate having a main surface, a semiconductor chip deposited to be opposed to the main surface of the conductive plate, and a bonding layer including porous sintered material and arranged between the conductive plate and the semiconductor chip, wherein a first outer edge of a bonding interface between the bonding layer and the conductive plate is located on the inside of an outer circumference of the semiconductor chip and is located on the inside of a second outer edge of a bonding interface between the bonding layer and the semiconductor chip.


