Sintered Conductive Matrix on Wire Bond Bumps
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Solution Overview
Problem
Existing microelectronic interconnection technologies, such as wire bonding and flip-chip mounting, result in larger assemblies due to the need for extensive fan-out connections and are prone to thermal stress and fatigue, limiting their compactness and reliability, especially in portable devices requiring high-density chip integration.
Innovation Solution
A microelectronic package utilizing metal bumps with conductive matrix material that contacts both ends and lateral surfaces, providing a compact and robust interconnection system that minimizes size and thermal stress by using a conductive matrix material to join metal bumps with microelectronic element contacts, allowing for efficient electrical connections without significant size increase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If wire bonding or TAB processes are used to connect microelectronic device contacts to substrate pads, then electrical connections can be established, but the assembly size increases significantly due to the need for fan-out connections outside the chip area
Solution Approach 1:
The patent transitions from planar fan-out connections to three-dimensional vertical interconnections by forming conductive posts through the substrate thickness. This dimensional change allows contacts to connect directly to underlying pads without requiring lateral fan-out, thereby reducing assembly size while maintaining connection reliability through the vertical conductive path.
Solution Approach 2:
The conductive posts are formed within and through the substrate layers, nesting the connection structure inside the substrate volume rather than extending outward. This nesting approach eliminates the need for external fan-out traces and reduces the overall assembly footprint while preserving electrical connectivity.
2Volume of moving object
If flip-chip mounting with solder bonds is used to achieve compact assembly, then assembly size is minimized, but thermal stress and fatigue failure occur due to rigid bonds unable to accommodate thermal expansion differences
Solution Approach 1:
The patent employs a compliant underfill material that fills the space between the chip and substrate, acting as a flexible buffer that can accommodate thermal expansion differences. This compliant layer prevents stress concentration at the rigid solder joints while maintaining the compact flip-chip configuration.
Solution Approach 2:
The underfill material serves as an intermediary between the rigid chip/substrate structure and the thermal expansion forces. It mediates the thermal stress by providing a compliant interface that absorbs expansion differences, thereby protecting the rigid solder bonds from fatigue failure.
3Reliability
If extensive fan-out connections are used to connect all chip contacts to substrate pads, then complete electrical connectivity is achieved, but the assembly area becomes substantially larger than the chip area
Solution Approach 1:
The patent utilizes the vertical dimension by forming conductive posts that extend through the substrate thickness. This allows electrical connections to be made in the vertical direction rather than requiring lateral fan-out, thereby achieving complete electrical connectivity while minimizing the horizontal assembly area.
Solution Approach 2:
The substrate is designed with localized conductive posts positioned directly beneath each chip contact, providing connectivity only where needed rather than requiring comprehensive fan-out to all substrate edges. This localized approach reduces the assembly area while maintaining necessary electrical connections.
4Strength
If rigid solder bonds are used in flip-chip mounting, then strong mechanical attachment is achieved, but fatigue failure occurs under thermal cycling due to inability to accommodate differential thermal expansion
Solution Approach 1:
The patent creates a composite structure combining rigid solder bonds for mechanical strength with a compliant underfill material for stress relief. This composite approach allows the assembly to maintain strong mechanical attachment while accommodating thermal expansion differences, thereby resisting fatigue failure under thermal cycling.
Solution Approach 2:
The compliant underfill material is applied beforehand to fill the space between chip and substrate, creating a cushioning layer that prevents stress concentration at the solder joints during thermal cycling. This prior cushioning protects the rigid bonds from fatigue while maintaining mechanical strength.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables a compact and reliable microelectronic assembly with reduced thermal stress and improved connectivity, enhancing the performance and reliability of high-density chip integration in portable devices by providing short, low-impedance interconnects without increasing assembly size.
Implementation Method 1
A sintering process is performed to sinter the conductive matrix material and form a conductive matrix
Data Source
AI summary
A method is disclosed of fabricating a microelectronic package comprising a substrate overlying the front face of a microelectronic element. A plurality of metal bumps project from conductive elements of the substrate towards the microelectronic element, the metal bumps having first ends extending from the conductive elements, second ends remote from the conductive elements, and lateral surfaces extending between the first and second ends. The metal bumps can be wire bonds having first and second ends attached to a same conductive pad of the substrate. A conductive matrix material contacts at least portions of the lateral surfaces of respective ones of the metal bumps and joins the metal bumps with contacts of the microelectronic element.