Sinusoidal Oxide MIM Capacitor Structure for Higher Capacitance Density
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Solution Overview
Problem
The fabrication of metal insulator metal (MIM) capacitors is challenging due to limited dielectric material selection, which can lead to reduced capacitance per area and increased component size, ultimately limiting semiconductor processing yield and space availability for other components.
Innovation Solution
A semiconductor device fabrication process that involves depositing an oxide layer on top of a metal layer, forming a photoresist layer with repeating spacing to define an oscillating wave structure, and etching trenches with rounded corners to increase the frequency and depth of the oscillating pattern, thereby enhancing capacitance per area density of the MIM capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional parallel plate MIM capacitor structure is used, then fabrication process is simple, but capacitance per area density is reduced and component size increases
Solution Approach 1:
The patent applies curvature by forming sinusoidal or oscillating wave patterns in the capacitor plates instead of using flat parallel plates. This curved/oscillating structure increases the effective surface area of the plates within the same footprint, thereby increasing capacitance per area density while maintaining compatibility with standard fabrication processes
Solution Approach 2:
The patent transitions from a two-dimensional flat plate structure to a three-dimensional oscillating structure by adding vertical undulations to the plates. This dimensional change allows the capacitor to achieve higher capacitance density by utilizing the third dimension (height/depth) to increase effective plate area without increasing the horizontal footprint
2Quantity of substance
If dielectric layer size is increased to provide necessary capacitance density, then capacitance per area is improved, but available space for other components is reduced
Solution Approach 1:
By forming sinusoidal or oscillating wave patterns in the capacitor plates, the patent increases the effective surface area of the plates within the same horizontal footprint. This curved structure allows the capacitor to achieve higher capacitance per area density without expanding the dielectric layer size or occupying more space on the semiconductor substrate
Solution Approach 2:
The patent utilizes the vertical dimension by creating oscillating plate structures that extend upward and downward from the substrate plane. This allows the capacitor to pack more capacitance into a smaller horizontal footprint by exploiting the third dimension, thereby maintaining high capacitance density while minimizing the area occupied on the chip
3Ease of manufacture
If more insulating material is etched to reach bottom metal plate, then via connection is achieved, but etch stop problems increase
Solution Approach 1:
The patent forms a sacrificial mandrel structure before depositing the dielectric layer. This mandrel defines the oscillating pattern and serves as a template for subsequent etching steps. By preparing this structure in advance, the patent enables precise control of the oscillating pattern formation and facilitates easier via etching with reduced risk of etch stop problems
Solution Approach 2:
The patent introduces a sacrificial mandrel as an intermediary structure during fabrication. This mandrel is temporarily formed to define the oscillating pattern, then removed after the dielectric is deposited. The mandrel acts as a mediator that enables precise pattern formation and controlled etching, reducing etch stop issues while maintaining the desired capacitor structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process effectively increases the capacitance per area density of MIM capacitors, manages semiconductor processing yield, and optimizes space usage by reducing the size of MIM capacitors while maintaining performance.
Implementation Method 1
places an oxide layer on top of a metal layer
Implementation Method 2
A photoresist layer is formed on top of the oxide layer and etched with repeating spacing which determines a frequency of an oscillating wave structure
Implementation Method 3
Trenches are etched into areas of the oxide layer unprotected by the photoresist layer
Data Source
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AI summary
A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places an oxide layer on top of a metal layer. A photoresist layer is formed on top of the oxide layer and etched with repeating spacing. One of a variety of lithography techniques is used to alter the distance between the spacings. The process etches trenches into areas of the oxide layer unprotected by the photoresist layer and strips the photoresist layer. The top and bottom corners of the trenches are rounded. The process deposits a bottom metal, a dielectric, and a top metal on the oxide layer both on areas with the trenches and on areas without the trenches. The process completes the metal insulator metal capacitor with metal nodes contacting each of the top plate and the bottom plate.