Sinusoidal Phase Adjustment Circuit for Wide-Frequency Operation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing phase adjustment circuits for sine waves are limited in their ability to operate across a wide range of frequencies, particularly due to the use of Quadrature-VCOs which have lower oscillation frequencies and 90-degree hybrids that operate only at specific frequencies.
Innovation Solution
A phase adjustment circuit comprising a clock generation unit, a delay unit, first and second multiplying units, and an adding unit, which allows for the generation of sinusoidal clock signals and arbitrary phase waveforms without relying on conventional Quadrature-VCOs or 90-degree hybrids, enabling operation across a wide frequency range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a Quadrature-VCO is used to generate sine waves with a fixed phase difference of π/2, then the phase adjustment can be achieved, but the oscillation frequency is limited to lower frequencies
Solution Approach 1:
The patent changes the fundamental approach from using a Quadrature-VCO with fixed π/2 phase difference to using a variable delay line that can adjust delay time continuously. This parameter change allows the system to achieve any phase difference (0 to 2π) without being constrained by the fixed architecture of Quadrature-VCO, thereby enabling operation at higher oscillation frequencies while maintaining precise phase control capability
Solution Approach 2:
The patent introduces a dynamic delay time adjustment mechanism where the delay time can be varied continuously based on the desired phase difference. This dynamic capability replaces the static π/2 fixed phase difference of Quadrature-VCO, allowing the system to adapt to any frequency requirement while maintaining accurate phase adjustment through the relationship: phase difference = 2π × delay time / period
2Measurement precision
If a 90 degree hybrid is used to produce a sine wave with a fixed phase difference of π/2, then the phase adjustment can be achieved, but it operates only at a specific frequency
Solution Approach 1:
The patent creates a universal phase adjustment circuit that can operate at any frequency by replacing the frequency-specific 90 degree hybrid with a variable delay line. The delay line can be adjusted to provide any required phase difference regardless of the operating frequency, making the circuit universally applicable across a wide frequency range while maintaining the ability to achieve precise phase adjustment
Solution Approach 2:
The patent changes the fixed delay characteristic of the 90 degree hybrid to a variable delay time parameter that can be adjusted continuously. This allows the system to maintain accurate phase adjustment (0 to 2π) across different frequencies by adapting the delay time to the specific frequency requirement, rather than being constrained to a single operating frequency
3Measurement precision
If conventional phase adjustment circuits are used, then phase adjustment can be achieved, but the circuit area, cost, and power consumption increase
Solution Approach 1:
The patent extracts the essential function of phase adjustment from complex conventional circuits (Quadrature-VCO, 90 degree hybrid) and implements it using a simpler variable delay line combined with amplitude control. This extraction removes unnecessary circuit complexity while retaining the core phase adjustment capability, thereby reducing circuit area, cost, and power consumption
Data Source
AI summary
In some implementations, the device may include a clock generator configured to generate a sinusoidal clock signal. The device may include a delay circuit configured to delay a signal output from the clock generator. The device may also include a first multiplier configured to output a signal obtained by multiplying an amplitude of the signal output from the clock generator by a first constant. Additionally, the device may include a second multiplier configured to output a signal obtained by multiplying an amplitude of the signal output from the delay circuit by a second constant. Also, the device may include an adder configured to add the signal output from the first multiplier and the signal output from the second multiplier.