SiO2 Interfacial Layer Regrowth Control in High-K Gate Structures
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Solution Overview
Problem
Current high-K gate structures in field effect transistors face challenges in achieving the desired capacitance equivalent thickness and homogeneous growth of high-K dielectric layers, leading to limitations in gate insulation thickness and increased gate leakage effects.
Innovation Solution
Incorporating a regrowth inhibiting agent, such as impurity ions like As or P, into the SiO2 interfacial layer to prevent regrowth during annealing, allowing for thinner gate insulation by controlling the thickness of both the interfacial and high-K dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the thickness of the gate insulating layer is reduced to meet ITRS requirements, then the gate capacitance equivalent thickness is improved, but gate leakage increases and homogeneous growth of the high-K dielectric layer becomes difficult
Solution Approach 1:
The gate insulating structure uses a composite of SiO2 interfacial layer and high-K dielectric layer (HfO2, HfSiO, or HfSiON). This composite structure allows achieving equivalent oxide thickness of 8Å or less while maintaining lower gate leakage compared to pure SiO2, as the high-K material provides higher capacitance per unit thickness
Solution Approach 2:
The patent applies different materials with different properties at different locations: SiO2 at the interface with the channel region for excellent interface quality and homogeneous nucleation, and high-K dielectric material above it for high capacitance. This local differentiation allows the system to achieve both low effective thickness and acceptable leakage
2Length of stationary object
If the thickness of the high-K dielectric layer is reduced below 12-15 Å, then the overall gate insulation thickness is reduced, but homogeneous growth of the high-K dielectric layer cannot be achieved
Solution Approach 1:
The SiO2 interfacial layer is formed first before depositing the high-K dielectric layer. This preliminary SiO2 layer acts as a seed layer that enables homogeneous nucleation and growth of the high-K dielectric material, allowing the high-K layer to be deposited at thicknesses below 12-15 Å while maintaining homogeneous structure
Solution Approach 2:
The SiO2 interfacial layer serves as an intermediary between the silicon substrate and the high-K dielectric layer. It provides a suitable interface for homogeneous nucleation of the high-K material, enabling thin high-K layers to grow uniformly without direct contact with the silicon substrate
3Manufacturing precision
If the interfacial layer thickness is increased to ensure homogeneous growth, then the overall gate insulation thickness increases, but the gate capacitance equivalent thickness requirement cannot be met
Solution Approach 1:
The composite structure of thin SiO2 interfacial layer (providing homogeneous growth) and thin high-K dielectric layer (providing high capacitance) allows achieving the desired capacitance equivalent thickness without requiring a thick interfacial layer. The high-K material's superior dielectric constant compensates for the reduced total thickness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the achievement of thinner gate insulation while maintaining effective gate capacitance, reducing gate leakage and aligning with the International Technology Roadmap for Semiconductors' requirements.
Implementation Method 1
introducing a regrowth inhibiting agent into the SiO2 layer
Implementation Method 2
High-K dielectric materials allow thicker insulating layer dimensions to be employed, while retaining relatively high values of gate capacitance
Data Source
AI summary
A field effect transistor having a gate structure comprising a high-K dielectric layer, a gate electrode located on the high-K dielectric layer, and an interfacial layer located in between the high-K dielectric layer and a channel region of the field effect transistor. The interfacial layer comprises a layer of SiO2 containing a regrowth inhibiting agent. A method of forming the gate structure includes forming a gate stack comprising, in order: a SiO2 layer adjacent a channel region of the field effect transistor; a high-K dielectric layer on the SiO2 layer; and a gate electrode on the high-K dielectric layer. The method also includes introducing a regrowth inhibiting agent into the SiO2 layer and then annealing the gate structure. The presence of the regrowth inhibiting agent in the SiO2 interfacial layer inhibits regrowth of the SiO2 layer into the channel region during the annealing step.