Self-Aligned SiON Bottom Spacer for Vertical Transistors
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Solution Overview
Problem
In semiconductor device fabrication, existing methods for forming gate spacers in vertical transistors face challenges such as nitridation of silicon oxide sidewalls, leading to non-selective etching and loss of gate controllability, and silicon nitride spacers can cause meniscus-shaped bottom spacers, affecting device performance.
Innovation Solution
A method is developed to form a self-aligned silicon oxynitride (SiON) bottom spacer by reacting germanium oxide with silicon germanium and annealing to create a silicon oxide layer, which is then nitrided to form a stable SiON spacer, ensuring uniform thickness and preventing fin hard mask and bottom spacer loss during removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If silicon oxide sidewalls are used for gate spacers, then etching selectivity is improved, but nitridation occurs leading to non-selective etching and loss of gate controllability
Solution Approach 1:
The patent uses a composite bottom spacer structure consisting of a silicon germanium layer and a silicon oxide layer. The silicon germanium layer serves as a nitridation-resistant barrier that prevents nitrogen diffusion into the silicon oxide sidewalls, while the silicon oxide layer provides the desired etching selectivity. This composite structure resolves the contradiction by combining materials with complementary properties.
Solution Approach 2:
The silicon germanium layer acts as an intermediary barrier between the nitrogen-containing etch chemistry and the silicon oxide sidewalls. It intercepts and prevents the harmful nitridation reaction while allowing the silicon oxide to maintain its spacer function, thus mediating between the conflicting requirements of etching selectivity and gate controllability.
2Stability of the object's composition
If silicon nitride spacers are used, then spacer stability is improved, but meniscus-shaped bottom spacers form affecting device performance
Solution Approach 1:
The patent employs a composite bottom spacer with a silicon germanium layer providing structural stability and a silicon oxide layer providing uniform conformal deposition. The silicon oxide layer is deposited conformally over the silicon germanium layer, ensuring uniform thickness without meniscus formation, while the underlying silicon germanium provides the necessary stability.
Solution Approach 2:
The patent applies different material properties to different parts of the bottom spacer structure. The silicon germanium layer provides local nitridation resistance and structural support, while the silicon oxide layer provides local etching selectivity and uniform conformal deposition. This local differentiation of material qualities resolves the contradiction between stability and shape uniformity.
3Device complexity
If self-aligned bottom spacer formation is achieved, then manufacturing complexity is reduced, but additional annealing and nitridation steps are required
Solution Approach 1:
The patent combines multiple functions into the bottom spacer formation process. The annealing step simultaneously activates dopants, forms the silicon oxide layer through reaction, and prepares the structure for nitridation. The subsequent nitridation step forms both the protective oxide layer and the final spacer material. This merging of steps reduces overall process complexity despite adding specific treatment steps.
Solution Approach 2:
The bottom spacer structure is self-aligned through the conformal deposition process. The silicon oxide layer automatically conforms to the underlying silicon germanium layer and fin structures, creating self-aligned spacers without requiring additional patterning steps. This self-alignment mechanism reduces manufacturing complexity while the chemical reactions provide the necessary material transformations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides a predictable and accurate channel length for both NFET and PFET devices, mitigating the issues of non-selective etching and meniscus-shaped spacers, and ensures equivalent spacer thickness without patterning, enhancing device performance and fabrication reliability.
Implementation Method 1
applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer
Implementation Method 2
The method includes annealing to chemically react the first silicon germanium layer with the germanium containing layer and form a silicon oxide layer
Implementation Method 3
The method includes performing a nitridation process to increase a nitrogen content of the silicon oxide layer and form a bottom spacer
Data Source
AI summary
A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.