SiOCN Spacer Carbon Grading for FinFET Parasitic Capacitance
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in effectively forming spacers for FinFETs, particularly in achieving optimal carbon and nitrogen concentrations in silicon oxycarbonitride (SiOCN) spacers to balance etching resistance and dielectric constant, which affects parasitic capacitance and device reliability.
Innovation Solution
The use of silicon oxycarbonitride (SiOCN) spacers with distinct carbon concentrations, where the first spacer has a higher carbon concentration than the second spacer, and varying nitrogen concentrations, while maintaining equal or different oxygen concentrations, to optimize etching resistance and dielectric properties during both isotropic and anisotropic etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If SiOCN spacers with high carbon concentration are used, then etching resistance is improved, but dielectric constant increases leading to higher parasitic capacitance
Solution Approach 1:
The patent applies local quality by forming a first SiOCN spacer layer with high carbon concentration (first carbon concentration) for etching resistance, and a second SiOCN spacer layer with low carbon concentration (second carbon concentration) for low dielectric constant. This spatial differentiation of material properties allows each layer to optimize its function: the first layer protects during etching while the second layer minimizes parasitic capacitance.
Solution Approach 2:
The patent uses composite materials by combining two SiOCN spacer layers with different carbon concentrations. The first SiOCN spacer layer has high carbon concentration for etching resistance, while the second SiOCN spacer layer has low carbon concentration for low dielectric constant. This composite structure resolves the contradiction between etching resistance and parasitic capacitance by integrating materials with complementary properties.
2Ease of manufacture
If single-layer SiOCN spacer is used, then manufacturing process is simple, but cannot simultaneously achieve high etching resistance and low dielectric constant
Solution Approach 1:
The patent applies segmentation by dividing the spacer structure into two distinct SiOCN spacer layers: a first SiOCN spacer layer with high carbon concentration for etching resistance, and a second SiOCN spacer layer with low carbon concentration for low dielectric constant. This segmentation allows independent optimization of etching resistance and dielectric properties, resolving the contradiction between process simplicity and performance requirements.
Data Source
AI summary
A semiconductor device includes a substrate including an active fin structure, a plurality of gate structures, a first spacer on sidewalls of each of the gate structures, and a second spacer on sidewalls of the first spacer. The active fin structure may extend in a first direction and including a plurality of active fins with adjacent active fins divided by a recess. Each of the plurality of gate structures may extend in a second direction crossing the first direction, and may cover the active fins. The first spacer may include silicon oxycarbonitride (SiOCN), and may have a first carbon concentration. The second spacer may include SiOCN and may have a second carbon concentration which is different from the first carbon concentration. The semiconductor device may have a low parasitic capacitance and good electrical characteristics.