Reducing Bypass Capacitors in System-in-Package Designs
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Solution Overview
Problem
Existing System-in-Package (SiP) designs often require more passive components than necessary due to vendor recommendations based on traditional PCB designs, leading to increased size and cost, as these recommendations do not account for the reduced electrical distance and component integration in SiP technology.
Innovation Solution
A method to determine and implement a reduced number and value of bypass capacitors in SiP designs by considering the shorter interconnection distances and component integration, allowing for fewer and smaller capacitors while maintaining performance, and potentially adding more active components without increasing the substrate area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vendor recommended numbers and values of bypass capacitors are used in SiP designs, then voltage supply quality is maintained, but the number of passive components and substrate area increase
Solution Approach 1:
The patent applies parameter changes by adjusting the number and values of bypass capacitors based on the specific electrical distance characteristics of SiP designs. Instead of using fixed vendor recommendations, the methodology calculates optimal capacitor parameters (number and capacitance value) according to the reduced interconnection distances in SiP, thereby maintaining voltage quality while reducing component quantity
Solution Approach 2:
The patent implements local quality by tailoring the bypass capacitor configuration to the specific local electrical characteristics of each SiP design. The methodology evaluates the actual electrical distance between power source and load in each specific SiP configuration and determines appropriate capacitor values locally, rather than applying universal vendor recommendations
2Reliability
If vendor recommended numbers and values of bypass capacitors are used in SiP designs, then voltage supply quality is maintained, but substrate area increases
Solution Approach 1:
The patent reduces substrate area by changing the parameters of bypass capacitors (number and capacitance values) to match the reduced electrical distances in SiP designs. This parameter optimization allows using fewer and/or smaller capacitors, directly reducing the occupied substrate area while maintaining power supply integrity
3Ease of operation
If traditional PCB design recommendations are applied to SiP, then design simplicity is maintained, but space and cost savings are lost
Solution Approach 1:
The patent maintains design simplicity while achieving space savings by providing a systematic methodology that automatically adjusts capacitor parameters based on SiP electrical distance characteristics. The approach simplifies the decision-making process by offering clear calculation methods and guidelines for determining optimal capacitor values in SiP, eliminating the need for designers to manually optimize each component
Data Source
AI summary
Methods and systems for reducing the number of, and values of, passive components, such as capacitors, in System-in-Package devices below vendor recommendations for an active component are provided.