SiP Clock Synchronization Without Domain Crossing Latency
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Solution Overview
Problem
Conventional clock domain crossing logic in System-in-Package (SiP) devices causes significant latency penalties in high-performance applications, and existing DLL circuitry fails to operate properly at low frequencies, limiting its operational range to 300 MHz, which is inadequate for many high-performance start-up conditions.
Innovation Solution
The implementation of a flexible and low-latency solution for synchronous data communication between two devices within a single phase clock domain interface, using a source clock signal with adjustable frequency and phase alignment circuitry to compensate for delays, allowing operation down to low frequencies without clock domain crossings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional clock domain crossing logic is used in SiP devices, then data communication between devices is enabled, but significant latency penalties occur in high-performance applications
Solution Approach 1:
The patent merges the clock domains of multiple SiP devices by distributing a single source clock signal to all devices, eliminating the need for clock domain crossing logic. This unification allows synchronous data communication without the latency penalties associated with conventional clock domain crossing approaches.
Solution Approach 2:
The patent extracts and removes the clock domain crossing logic from the system by implementing a shared source clock signal that eliminates the need for separate clock domains. This extraction eliminates the inherent latency of clock domain crossing while maintaining data communication capability.
2Adaptability or versatility
If existing DLL circuitry is used for clock synchronization, then clock alignment is achieved, but operation below 300 MHz is not supported
Solution Approach 1:
The patent changes the operational parameters of the clock synchronization system by using a source clock signal with adjustable frequency that can operate below 300 MHz. This parameter change extends the operational frequency range while maintaining reliable clock synchronization through phase alignment circuitry designed to function at these lower frequencies.
3Loss of time
If a single source clock signal is distributed to multiple SiP devices, then synchronous communication is enabled without latency penalties, but clock skew and phase alignment challenges arise
Solution Approach 1:
The patent introduces phase alignment circuitry as an intermediary component at each SiP device that receives the source clock signal and adjusts its phase locally. This intermediary mechanism compensates for clock skew introduced by different distribution path lengths, enabling synchronous communication without latency penalties while overcoming phase alignment challenges.
Data Source
AI summary
A source clock signal is received from a primary semiconductor device by a secondary semiconductor device via an interconnect. A local clock signal is generated on the secondary semiconductor device based on the source clock signal. A mode control signal is generated on the secondary semiconductor device, where the mode control signal indicates one of an unlock mode of operation and a lock mode of operation of the secondary semiconductor device. A physical interface (PHY) clock signal is generated based on the local clock signal, where the PHY clock signal includes the local clock signal during the lock mode, and the PHY clock signal includes an inverted version of the local clock signal during the unlock mode. Data received from the primary semiconductor device via the interconnect is latched at a positive edge of the PHY clock signal during the unlock mode and the lock mode.