System in Package Integrating Common and Custom Semiconductor Chips
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Solution Overview
Problem
Current System on Chip (SoC) technologies face challenges in efficiently integrating common and individual functions within a single semiconductor chip, leading to lengthy development periods and high costs due to the need for redesigning components with changes in chip position or size, and require complex processes like solder reflow for chip mounting.
Innovation Solution
A System in Package (SiP) that integrates a common CPU chip and a custom chip with different wiring layers, connected by bonding wires on a module substrate with a common shape, allowing for easy reconfiguration of the custom chip's wiring layer to implement individual functions without the need for redesigning the substrate or using complex mounting processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a System on Chip (SoC) integrates all functional blocks in one semiconductor chip, then all functions can be implemented in one semiconductor process, but it requires designing and manufacturing a semiconductor chip for each user, leading to long development periods and high development costs
Solution Approach 1:
The system is divided into a common chip (containing CPU and standard functional blocks) and an individual chip (containing user-specific functional blocks). This segmentation allows the common chip to be manufactured once and reused across multiple products, while only the individual chip needs customization for each user, significantly reducing development time and cost.
Solution Approach 2:
The common chip is designed to be universal and can be used in multiple different system in packages for different users. By making the common chip multi-functional and reusable, the patent eliminates the need to redesign the entire system for each user, thus reducing development period and cost while maintaining adaptability.
2Adaptability or versatility
If a System on Chip (SoC) integrates all functional blocks in one semiconductor chip, then all functions can be implemented in one semiconductor process, but it requires high development cost
Solution Approach 1:
The system is divided into a common chip (containing CPU and standard functional blocks) and an individual chip (containing user-specific functional blocks). This segmentation allows the common chip to be manufactured once and reused across multiple products, while only the individual chip needs customization for each user, significantly reducing development time and cost.
Solution Approach 2:
The common chip is designed and manufactured in advance before the individual customization is needed. This preliminary action allows the expensive common functionality to be developed once and reused, reducing the overall development cost for each customized product.
3Quantity of substance
If chip size is increased to mount high-capacity memory, then high-capacity memory can be integrated, but the percentage of non-defective items decreases significantly
Solution Approach 1:
The system is divided into a common chip (containing CPU and standard functional blocks) and an individual chip (containing user-specific functional blocks). This segmentation allows the common chip to be manufactured once and reused across multiple products, while only the individual chip needs customization for each user, significantly reducing development time and cost.
4Adaptability or versatility
If lamination structure is used to integrate main chip and sub chip, then chips can be integrated into one package, but redesign of main chip is required when sub chip position or size changes
Solution Approach 1:
A module substrate is introduced as an intermediary between the common chip and the individual chip. The module substrate provides a standardized interface and mounting structure, allowing the individual chip to be replaced or reconfigured without affecting the common chip. This intermediary absorbs the complexity of adaptation, eliminating the need to redesign the main chip when sub chip position or size changes.
5Area of stationary object
If high-density integration is achieved by face-down positioning of CSP chips, then space between adjacent chips is reduced, but complex mounting processes are required
Solution Approach 1:
A module substrate is introduced as an intermediary between the common chip and the individual chip. The module substrate provides a standardized interface and mounting structure, allowing the individual chip to be replaced or reconfigured without affecting the common chip. This intermediary absorbs the complexity of adaptation, eliminating the need to redesign the main chip when sub chip position or size changes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the rapid design and manufacturing of customized products with both common and individual functions at a lower development cost, reducing manufacturing time and eliminating the need for complex solder reflow processes, while allowing for flexible chip size adjustments without altering the module substrate.
Implementation Method 1
the first module connection terminal and the second module connection terminal are connected by a bonding wire
Data Source
AI summary
A system in package integrating a plurality of semiconductor chips, including a first chip mounted commonly in a plurality of system in packages and at least including a CPU, a second chip having a different specification for each of the plurality of system in packages depending on a connection of internal lines, and a module substrate including the first chip and the second chip adjacent to each other and having a shape common to the plurality of system in packages. The first chip includes a first module connection terminal on the first chip along a first side facing the second chip or in an area different from the first chip and facing the second chip. A second side of the second chip includes a second module connection terminal to be connected with the first chip. The first and the second module connection terminals are connected by a bonding wire.