SIP Inductor Manufacturing via Penetration Electrodes
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Solution Overview
Problem
Conventional semiconductor device manufacturing processes face challenges in minimizing parasitic resistance and capacitance in inductors, leading to decreased characteristic factors and performance issues in RF chips, especially due to complex process conditions and interference from induced magnetic fields.
Innovation Solution
A method for manufacturing an inductor using a system-in-package (SIP) involves patterning a silicon substrate, depositing barrier metals, burying metal materials, and planarizing to form electrodes, while also allowing for independent manufacturing and connection of inductors and transistors, thereby reducing parasitic effects and magnetic interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal film is formed with a large thickness to reduce parasitic resistance, then the inductance value is maintained, but the process condition becomes complicated and manufacturing precision deteriorates
Solution Approach 1:
The patent divides the inductor manufacturing into separate stages: first forming a penetration electrode through the substrate, then forming the inductor coil structure, and finally connecting them. This segmentation allows each component to be optimized independently, avoiding the need for complex thick metal film formation while maintaining low parasitic resistance through the penetration electrode design.
Solution Approach 2:
The patent introduces a vertical dimension by creating penetration electrodes that extend through the substrate thickness. This three-dimensional approach allows current to flow through the substrate depth rather than relying solely on thick surface metal films, reducing parasitic resistance without complicating the planar manufacturing process.
2Adaptability or versatility
If the inductor is formed on the same substrate as transistors and metal wiring, then integration is achieved, but the induced magnetic field interferes with the current in metal wiring
Solution Approach 1:
The patent extracts the inductor structure from the conventional planar substrate surface and positions it in a three-dimensional configuration using the penetration electrodes. This spatial separation reduces the magnetic coupling between the inductor and underlying metal wiring, minimizing interference while maintaining integration on the same substrate.
Solution Approach 2:
The penetration electrodes act as intermediaries between the substrate and the inductor coil. By routing current through these vertical electrodes rather than through planar metal wiring beneath the inductor, the patent eliminates the direct magnetic coupling path, reducing interference while maintaining electrical connectivity.
3Area of stationary object
If the area occupied by the inductor is minimized for high integration, then the RF chip area is reduced, but the inductance value becomes difficult to maintain
Solution Approach 1:
The patent transitions from a two-dimensional planar inductor to a three-dimensional structure using vertical penetration electrodes. This allows the inductor to achieve its inductance value through vertical current paths and magnetic flux containment, maintaining the required inductance in a smaller footprint area suitable for high integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces parasitic resistance and capacitance, and minimizes the impact of induced magnetic fields, enhancing the performance and integration of RF devices by allowing independent fabrication and connection of inductors and transistors.
Implementation Method 1
depositing a first barrier metal in an inner wall of the first penetration hole
Implementation Method 2
burying a first metal material in the penetration hole
Implementation Method 3
planarizing the metal material to form a first penetration electrode
Implementation Method 4
depositing an insulating film on a first surface of the silicon substrate
Implementation Method 5
performing a back grind process such that the first penetration electrode is exposed from a second surface of the silicon substrate
Data Source
AI summary
A method for manufacturing an inductor using a system-in-package (SIP) includes forming a first penetration electrode in a silicon substrate; depositing an insulating film on a first surface of the silicon substrate, and patterning the insulating film to form an inductor hole and a second penetration hole aligned with the first penetration hole; forming an inductor in the inductor hole and a second penetration electrode in the second penetration hole; and depositing a protective film on the insulating film and performing a back grind process such that the first penetration electrode is exposed from a second surface of the silicon substrate, the second surface being opposed to the first surface.