SiP and IO Board Stacking for Compact Signal-Robust Integration
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Solution Overview
Problem
Existing methods for integrating System in Package (SiP) with Input/Output (IO) boards in mobile devices face challenges in miniaturization, as they often compromise on size, cost, and electrical performance due to the use of flexible printed circuits (FPC) connectors, which are costly and lead to real estate waste and signal integrity issues.
Innovation Solution
The proposed solution involves eliminating FPC connectors and flex cables by stacking the SiP directly onto the IO board using Ball Grid Array (BGA) or Land Grid Array (LGA) interconnects, allowing for a more compact design without compromising the Z dimension, and optimizing component placement on both sides of the SiP to reduce overall size while maintaining electrical robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FPC connectors and flex cables are used to integrate SiP with IO board, then electrical connection is achieved, but real estate is wasted and signal integrity deteriorates
Solution Approach 1:
The patent extracts and eliminates the FPC connectors and flex cables from the integration system, replacing them with a direct stacking architecture. This removal of intermediate components simultaneously improves signal integrity by eliminating signal loss pathways and recovers real estate that was previously occupied by these components and their routing paths.
Solution Approach 2:
The patent merges the SiP and IO board into a single stacked unit, eliminating the separate connection components (FPC connectors and flex cables). This consolidation achieves direct electrical connection between the SiP and IO board, improving signal integrity while reducing the overall area required for the integration.
2Reliability
If FPC connectors are used for SiP integration, then electrical connection is established, but manufacturing cost increases
Solution Approach 1:
The patent removes the expensive FPC connectors from the bill of materials and replaces them with standard BGA/LGA interconnect technologies. This extraction eliminates the need for specialized high-cost components while maintaining reliable electrical connection through conventional, cost-effective packaging techniques.
Solution Approach 2:
The patent replaces expensive, specialized FPC connector components with more economical standard BGA/LGA interconnect solutions. These standard interconnect technologies are widely available, cost-effective, and achieve the same electrical connection function without the premium cost associated with FPC connectors.
3Adaptability or versatility
If conventional SiP integration methods are used, then device functionality is achieved, but device size remains large
Solution Approach 1:
The patent transitions from a planar integration layout to a three-dimensional stacked architecture. By stacking the SiP directly onto the IO board vertically, the design utilizes the Z-dimension for integration, thereby reducing the XY-footprint and overall device size while maintaining full functionality through the vertical interconnect structure.
Solution Approach 2:
The patent implements a nested configuration where the SiP is positioned directly on top of the IO board, with one or both components potentially featuring openings that allow components to be positioned within the other component's footprint. This nesting approach maximizes space utilization and minimizes the overall device volume.
Data Source
AI summary
Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.