System-in Package Memory DQ Pad Connection Mapping
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Solution Overview
Problem
Manufacturers face difficulties in testing and failure analysis of system-in packages due to lack of shared information on connection configurations between DQ pads of semiconductor memory devices and input/output pins, hindering effective testing and analysis.
Innovation Solution
A system-in package with a semiconductor memory device that generates internal clocks and DQ information signals when in test mode, allowing for the determination of connection configurations by outputting these signals to DQ pads and input/output pins, facilitating testing and analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If connection configuration information is not shared between manufacturers, then manufacturing independence is maintained, but testing and failure analysis become difficult
Solution Approach 1:
The patent implements a test mode that performs connection configuration determination before actual product testing or failure analysis. By pre-establishing the mapping between DQ pads and input/output pins through automated testing procedures, the system prepares connection information in advance, making subsequent testing and failure analysis straightforward without requiring information sharing between manufacturers.
2Difficulty of detecting and measuring
If connection configuration information is shared between manufacturers, then testing and failure analysis become easy, but information security and manufacturing independence are compromised
Solution Approach 1:
The patent introduces an automated test mode as an intermediary mechanism that determines connection configurations without requiring direct information exchange between manufacturers. The test mode acts as a neutral mediator that automatically maps DQ pads to input/output pins through sensing and determination procedures, enabling testing and failure analysis while keeping proprietary connection information confidential within each manufacturer's domain.
3Loss of information
If manual determination of connection configurations is performed, then information security is maintained, but testing efficiency and productivity are reduced
Solution Approach 1:
The patent enables the system to determine connection configurations automatically through a built-in test mode that senses output levels from DQ pads and autonomously establishes the mapping to input/output pins. This self-service capability eliminates the need for manual information exchange or manual determination procedures, achieving both information protection and high testing efficiency through automated self-determination within the semiconductor memory device.
Data Source
AI summary
A semiconductor memory device includes an internal clock generation unit configured to generate an internal clock including periodic pulses during a period of a test mode; a DQ information signal generation block configured to generate DQ information signals which are sequentially enabled, in response to the internal clock; and a data output block configured to output the DQ information signals to DQ pads during a period of the test mode.