System-in-Package Memory Layout for Shorter Signal Paths
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Solution Overview
Problem
System-in-package modules face challenges in achieving improved reliability and signal integrity due to variations in component performance and placement, which affects their overall performance and size efficiency.
Innovation Solution
The implementation of a system-in-package module with fan-in wafer level package (FI-WLP) memories strategically placed around an ASIC chip on a substrate, connected through solder balls, and surrounded by a mold, ensures close proximity and optimized signal paths, enhancing signal integrity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional FBGA packages are used, then module size is larger, but signal integrity deteriorates due to longer signal paths
Solution Approach 1:
The patent transitions from a two-dimensional planar layout (FBGA) to a three-dimensional stacked configuration where memory chips are positioned vertically above the ASIC chip. This dimensional change enables shorter signal paths while maintaining a compact footprint, achieving both improved signal integrity and reduced module size.
Solution Approach 2:
The patent implements a nested structure where memory chips are stacked directly on top of the ASIC chip, with multiple layers utilizing vertical space. This nesting approach consolidates components into a compact volume, reducing the overall module footprint while minimizing signal path lengths through direct vertical connections.
2Reliability
If components are spaced far apart on the substrate, then manufacturing is easier, but signal integrity deteriorates due to longer signal paths and increased interference
Solution Approach 1:
By moving from horizontal placement to vertical stacking, the patent reduces the horizontal distance between components to minimal values while maintaining manufacturability through standardized stacking processes. The vertical arrangement naturally minimizes signal path length without requiring extreme precision in lateral positioning.
Solution Approach 2:
The patent changes the spatial arrangement parameter from horizontal spacing to vertical stacking distance, which can be precisely controlled through thin-film deposition and bonding processes. This parameter change enables close proximity (improved signal integrity) while using well-established manufacturing techniques for vertical integration.
3Reliability
If component placement is not optimized, then device complexity is reduced, but signal integrity and performance deteriorate
Solution Approach 1:
The patent segments the system into distinct functional layers: an ASIC chip layer and memory chip layers stacked above it. This segmentation allows each layer to be optimized independently for its function while the vertical stacking provides straightforward interconnection, balancing performance optimization with manageable complexity.
Solution Approach 2:
The vertical stacking architecture serves multiple functions simultaneously: it reduces signal path length for improved signal integrity, minimizes module footprint for compactness, and provides a scalable platform for adding memory capacity by stacking additional layers. This multi-functionality achieves performance goals without proportionally increasing complexity.
Data Source
AI summary
A system-in-package module includes a substrate, an application specific integrated circuit (ASIC) chip on the substrate, first wafer level package (WLP) memories on the substrate spaced apart from the ASIC chip in a first direction parallel to an upper surface of the substrate, and second WLP memories on the substrate spaced apart from the ASIC chip in a direction opposite to the first direction.