System-in-Package Network Processor With On-Package Low-Latency Memory
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Solution Overview
Problem
Conventional solutions for data processing applications face limitations due to high cost and inefficiency in accessing high-capacity, low-latency memory, which affects the performance of systems like network switches, routers, and storage infrastructure.
Innovation Solution
A multi-die system-in-package (SiP) design integrates a network processor with a base die containing low-latency memory, utilizing a high-speed interface and network-on-chip (NOC) circuitry for efficient data exchange and dynamic reconfiguration, enabling sector-aligned memory for temporary storage and secure data communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If external memory devices are used to provide high capacity memory, then memory capacity is improved, but cost increases and latency increases
Solution Approach 1:
The patent merges the network processor and memory into a single integrated circuit device, with memory blocks directly coupled to the network processor through a memory interface. This integration eliminates the need for external memory devices, reducing both access latency and cost while providing sufficient memory capacity through on-chip memory blocks that can be configured in different modes (e.g., dual-port, single-port, deep-buffer modes).
Solution Approach 2:
The patent transitions from a two-dimensional external memory architecture to a three-dimensional integrated structure where memory blocks are embedded within the same chip as the network processor. This vertical integration approach reduces physical distance and signal propagation delays, achieving low-latency access while maintaining high capacity through stacked or distributed memory blocks.
2Productivity
If external memory devices are used to provide high bandwidth memory, then memory bandwidth is improved, but device complexity increases
Solution Approach 1:
By integrating memory blocks and the network processor on the same chip with direct coupling through a memory interface, the patent eliminates the need for complex external memory controllers, buses, and interface circuits. The on-chip memory interface provides high bandwidth through short interconnects while simplifying the overall system architecture by removing external memory devices and their associated complexity.
3Loss of time
If on-chip memory is used to reduce latency, then memory access latency is improved, but memory capacity is reduced
Solution Approach 1:
The patent implements dynamically reconfigurable memory blocks that can change their operational mode based on application requirements. Memory blocks can be configured as dual-port for simultaneous read/write operations, single-port for sequential access, or deep-buffer modes for packet buffering, allowing the system to optimize between latency and capacity dynamically rather than being fixed in a static configuration.
Solution Approach 2:
The integrated circuit device contains multiple independent memory blocks that can be individually configured and addressed. This segmentation allows the system to allocate different portions of total memory capacity to different applications or protocols, effectively providing both low-latency access for time-critical operations and high capacity for bulk data storage within the same on-chip architecture.
Data Source
AI summary
This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.