Dual-Sided SiP Packaging With TMVs for Fine-Pitch Interconnects

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Solution Overview

Problem

The semiconductor industry faces challenges in achieving high integration density and miniaturization of electronic components, particularly in forming interconnects with a smaller pitch without increased risk of bridging or process defects, while also requiring flexible design options and reduced warpage in package structures.

Innovation Solution

The implementation of a System-in-Package (SiP) device with an asymmetric dual-sided molded package on a multi-layered redistribution structure, utilizing through-molding vias (TMVs) and varying molding materials and thicknesses on each side to connect heterogeneous devices, allowing for a greater number of connections and improved reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If interconnects are formed with smaller pitch to increase connection density, then device functionality and integration density are improved, but the risk of bridging and process defects increases

Engineering Contradiction:
Improveconnection densityVSAvoidbridging risk
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The molding process is segmented into multiple stages with different materials (first molding material and second molding material) applied at different times. This segmentation allows for controlled formation of interconnect openings and prevents bridging by ensuring proper isolation between interconnect regions during the molding process.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Interconnect openings are formed and prepared before the second molding material is applied. This preliminary action ensures that interconnect structures are properly defined and isolated before final encapsulation, preventing bridging defects while enabling smaller pitch interconnect formation.

Inventive Principle:
Principle #10Preliminary action

2Stability of the object's composition

If molding material thickness is increased to reduce warpage, then package structural stability is improved, but package size and complexity increase

Engineering Contradiction:
Improvewarpage reductionVSAvoidpackage structure
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

Different molding materials with different thicknesses are applied to different regions of the package. The first molding material provides baseline encapsulation while the second molding material is applied selectively to regions requiring additional warpage control, achieving stability without uniform thickness increase.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The package structure employs asymmetric molding material distribution with varying thicknesses on different sides of the semiconductor device. This asymmetric design allows targeted warpage compensation while maintaining overall package compactness and reducing unnecessary material usage.

Inventive Principle:
Principle #4Asymmetry

3Stability of the object's composition

If asymmetric dual-sided molding with varying material thicknesses is used to reduce warpage, then package stability is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvepackage warpageVSAvoidmolding process
Core Design Contradiction:
Stability of the object's compositionVSEase of manufacture

Solution Approach 1:

The molding process is divided into sequential stages with distinct materials and thicknesses applied in a controlled manner. This segmentation transforms a complex single-step process into manageable stages, reducing manufacturing complexity while achieving warpage control.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12166025B2Semiconductor devices and methods of manufacturing
Publication Date: 2024.12.10 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12166025B2 patent drawing
  • US12166025B2 patent drawing
  • US12166025B2 patent drawing

AI summary

A method includes forming a redistribution structure including metallization patterns; attaching a semiconductor device to a first side of the redistribution structure; encapsulating the semiconductor device with a first encapsulant; forming openings in the first encapsulant, the openings exposing a metallization pattern of the redistribution structure; forming a conductive material in the openings, comprising at least partially filling the openings with a conductive paste; after forming the conductive material, attaching integrated devices to a second side of the redistribution structure; encapsulating the integrated devices with a second encapsulant; and after encapsulating the integrated devices, forming a pre-solder material on the conductive material.