System-in-package with segmented power supply regions

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Solution Overview

Problem

In stack packages, increasing the number of semiconductor chips leads to increased parasitic capacitance, hindering high-speed operation of input/output pads due to common power supply to output drivers, which affects data output speed.

Innovation Solution

A system-in-package design where each semiconductor chip has independent power supply regions for output drivers, controlled by a controller that selectively supplies power based on data output operations, reducing parasitic capacitance and enabling independent operation of output drivers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple semiconductor chips are stacked in a single package, then data storage capacity is increased, but parasitic capacitance of package pins increases which hinders high-speed operation

Engineering Contradiction:
Improvedata storage capacityVSAvoidparasitic capacitance
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The power supply system is segmented into multiple independent power supply pins, each dedicated to specific output drivers on individual semiconductor chips. This segmentation allows each chip to have its own power supply path, preventing the accumulation of parasitic capacitance from multiple chips sharing a common power supply, thereby maintaining high-speed operation while enabling increased data storage capacity through multi-chip stacking.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If common power supply is used for output drivers on multiple chips, then device complexity is reduced, but loading time of data input/output pads increases and output speed decreases

Engineering Contradiction:
Improvepower supply configurationVSAvoidloading time
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The power supply configuration is segmented into multiple independent power supply pins, with each pin connected to specific output drivers on individual chips. This allows independent power supply control for each chip, reducing the loading time of data input/output pads by eliminating the cumulative effect of parasitic capacitance from multiple chips sharing a common power supply, while maintaining manageable device complexity through systematic pin assignment.

Inventive Principle:
Principle #1Segmentation

3Quantity of substance

If more semiconductor chips are assembled in a stack package, then data storage capacity is improved, but parasitic capacitance increases which reduces output speed

Engineering Contradiction:
Improvedata storage capacityVSAvoidoutput speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The power supply system is segmented into multiple independent power supply pins, each dedicated to specific output drivers on individual semiconductor chips. This segmentation enables more chips to be stacked in the package to increase data storage capacity while maintaining high output speed by preventing parasitic capacitance accumulation through independent power supply paths for each chip.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9318469B2Stack package and system-in-package including the same
Publication Date: 2016.04.19 MIMIRIP LLC
  • US9318469B2 patent drawing
  • US9318469B2 patent drawing
  • US9318469B2 patent drawing

AI summary

A system-in-package includes first and second semiconductor chips disposed in a first region over a substrate, and a controller disposed in a second region over the substrate and selectively supplying a power supply voltage to the first or second semiconductor chip based on a data output operation of the first and second semiconductor chips, wherein each of the first and second semiconductor chips includes a first power supply region coupled with the controller through a first line and receiving the power supply voltage from the controller in common during an input/output operation of the first and second semiconductor chips, an output driver suitable for outputting data, and a second power supply region independently coupled with the controller through one of a second line and a third line and independently receiving the power supply voltage for an operation of the output driver from the controller during the data output operation.