SiP Stress-Inducing Layers for Transistor Carrier Mobility
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Solution Overview
Problem
As integrated circuits are scaled down, it becomes challenging to maintain or improve transistor performance, particularly in enhancing carrier mobility in PMOS and NMOS transistors through stress application in the channel region.
Innovation Solution
A semiconductor device fabrication method involving the formation of a gate structure, patterning a substrate to create a recess, and depositing stress-inducing SiP layers with varying phosphorus concentrations by selective epitaxial growth to apply tensile stress to the channel region, thereby increasing carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If integrated circuits are scaled down, then device size is reduced, but transistor performance deteriorates
Solution Approach 1:
The patent applies stress-inducing layers with different materials and properties to specific regions (source and drain regions) of the transistor, creating local quality variations that improve carrier mobility in the channel region without requiring overall device scaling reversal
Solution Approach 2:
The patent changes material parameters by introducing stress-inducing layers with different stress characteristics (tensile or compressive) to modify the physical state of the channel region, thereby improving transistor performance at scaled dimensions
2Reliability
If stress is applied to channel region, then carrier mobility is improved, but device complexity increases
Solution Approach 1:
The stress-inducing structure is segmented into multiple layers with different functions: a first stress-inducing layer providing initial stress and a second stress-inducing layer providing additional stress or stress adjustment, allowing independent optimization of each layer
Solution Approach 2:
The patent uses composite material structures combining different semiconductor materials (e.g., SiGe, SiC, or other group IV materials) with different lattice constants to generate controlled stress in the channel region through material composition rather than mechanical means
3Stress or pressure
If high phosphorus concentration is used in SiP layer, then stress effect is enhanced, but dislocations increase
Solution Approach 1:
The stress-inducing function is divided between two separate layers: the first SiP layer provides initial stress with lower phosphorus concentration, while the second SiP layer provides additional stress with higher phosphorus concentration, distributing the stress burden to avoid excessive doping in a single layer
Solution Approach 2:
Different regions of the stress-inducing structure have different phosphorus concentrations optimized for their specific functions: the first layer has lower phosphorus concentration to minimize dislocations while providing baseline stress, and the second layer has higher phosphorus concentration to enhance stress effect in regions where dislocation risk is managed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively increases carrier mobility and reduces defects, improving transistor performance by applying controlled stress through the use of SiP layers with different phosphorus concentrations, which enhances the electrical properties and reduces contact resistance.
Implementation Method 1
The buffer layer and the stress-inducing layer may be formed by selective epitaxial growth
Implementation Method 2
When suitable stress is applied to a channel region of a transistor, mobility of carriers in the channel region increases
Data Source
AI summary
A semiconductor device includes a substrate comprising a channel region and a recess, wherein the recess is located at both side of the channel region; a gate structure formed over the channel region; a first SiP layer covering bottom corners of the gate structure and the recess; and a second SiP layer formed over the first SiP layer and in the recess, wherein the second SiP layer has a phosphorus concentration higher than that of the first SiP layer.