SiP Package Substrate Edge Extension for Vertical Density
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in increasing vertical density while maintaining effective communication and thermal management between stacked chips in System in Package (SiP) configurations, leading to inefficiencies in space utilization and thermal performance.
Innovation Solution
The method involves a package substrate with conductive patterns and vias for signal and power distribution, combined with a thermal interface material and multiple die packages stacked on a substrate, where each die package extends beyond the edges of the substrate, allowing for electrical and mechanical connections via solder, and encapsulation with molding compound to enhance thermal conductance and reduce air gaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If chips are stacked vertically in SiP configuration to increase vertical density, then space utilization is improved, but thermal management becomes more difficult due to heat accumulation in stacked layers
Solution Approach 1:
A substrate is introduced as an intermediary component between stacked die packages to facilitate thermal management. The substrate provides thermal pathways and spacing that enable heat dissipation from multiple die packages stacked in vertical configuration, resolving the thermal management difficulty while maintaining high vertical density.
Solution Approach 2:
The patent transitions from horizontal chip arrangement to vertical stacking configuration, utilizing the vertical dimension to increase density. By stacking die packages vertically on the substrate rather than placing them horizontally, the design achieves higher space utilization while the substrate provides thermal management pathways in the vertical architecture.
2Volume of moving object
If multiple die packages are stacked closely to increase vertical density, then space utilization is improved, but effective communication between chips deteriorates due to signal interference and path complexity
Solution Approach 1:
The substrate serves as an intermediary platform that provides organized signal distribution pathways between stacked die packages. Conductive patterns on the substrate enable reliable electrical connections between chips in the vertical stack, maintaining communication effectiveness despite the increased vertical density and potential signal interference.
3Volume of moving object
If die packages are positioned to extend beyond substrate edges to maximize space utilization, then vertical density is improved, but manufacturing precision becomes more challenging due to alignment requirements
Solution Approach 1:
The design segments the overall package into the substrate and multiple die packages as separate manufacturable components. The substrate is manufactured with defined edge extensions, and die packages are separately prepared and then positioned on the substrate. This segmentation allows each component to be manufactured independently with standard precision, reducing the overall manufacturing difficulty compared to creating a fully integrated monolithic structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases vertical density, improves thermal performance, and ensures reliable electrical connections between stacked chips, addressing the inefficiencies in existing SiP technologies by optimizing space utilization and thermal management.
Implementation Method 1
thermal interface material and multiple die packages stacked on a substrate, where each die package extends beyond the edges of the substrate, allowing for electrical and mechanical connections via solder, and encapsulation with molding compound to enhance thermal conductance and reduce air gaps
Data Source
AI summary
A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate.