SiP Package Substrate Bonding for Direct Heat Dissipation
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Solution Overview
Problem
Current FOWLP packaging for SiP electronic chips faces inefficiencies in heat dissipation due to the use of external heatsinks and thermal interface materials, which are costly and limit thermal conduction performance.
Innovation Solution
An electronic device design where a substrate, secured to the chip and encapsulation material via direct-bonded metal layers, acts as a heat sink without the need for thermal interface materials, enhancing heat dissipation through improved thermal bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If external heat sinks and thermal interface materials are used for heat dissipation, then heat dissipation can be achieved, but the cost increases and thermal conduction performance is limited
Solution Approach 1:
The patent merges the heat dissipation function directly into the packaging structure by integrating the substrate as a heat sink and using metal layers as both interconnection and thermal conduction paths, eliminating the need for separate external heat sinks and thermal interface materials. This integration reduces component count and manufacturing cost while improving thermal performance.
Solution Approach 2:
The substrate and metal layers serve multiple functions: they provide both electrical interconnection and thermal conduction pathways. The first and second metal layers act as both interconnection structures and heat dissipation paths, eliminating the need for dedicated thermal management components and reducing overall system cost.
2Ease of operation
If thermal interface material is used between heat sinks and chips, then assembly is enabled, but thermal conduction is limited
Solution Approach 1:
The patent extracts and eliminates the thermal interface material from the thermal conduction path by establishing direct bonding between metal layers. The metal layers themselves provide both the mechanical bonding function previously requiring adhesive materials and the thermal conduction function, removing the thermal resistance introduced by interface materials.
Solution Approach 2:
The patent uses composite metal layer structures (including copper and gold layers with diffusion barriers) that provide both mechanical bonding strength and high thermal conductivity. These composite structures replace the combination of thermal interface materials and heat sinks, offering superior thermal conduction while maintaining assembly capability through direct bonding.
3Temperature
If individual heat sinks are coupled to chips, then heat dissipation is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges multiple heat dissipation functions into a single integrated substrate structure. Instead of coupling individual heat sinks to each chip, the substrate serves as a common heat sink for multiple chips, and the metal layers provide unified thermal conduction paths, significantly reducing structural complexity.
Solution Approach 2:
The substrate and metal layer structure serves universal functions for multiple chips: providing both electrical interconnection and thermal conduction for all chips in the package. This multi-functional design eliminates the need for individual heat sink assemblies for each chip, reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly improves heat dissipation performance by creating a robust thermal bond between the substrate and the chip, reducing costs associated with external heatsinks and thermal interface materials while enhancing thermal conductivity.
Implementation Method 1
the thermal connection formed by the first and second metal layers is much better than that obtained by using a thermal interface material such as an adhesive or thermal grease
Implementation Method 2
the role of heat sink is fulfilled by the substrate which is secured to the electronic chip and to the encapsulation material by means of the first and second metal layers
Data Source
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AI summary
A method for manufacturing a SiP-type electronic device, comprising: - transferring an electronic chip (100) onto a first substrate (102) such that one electrical interconnection face of the chip is disposed on the side of the first substrate; - encapsulating the chip in an encapsulation material (108); - creating at least one first metallic layer (112) on the encapsulation material and the chip; - creating at least one second metallic layer (114) on a second substrate (116); - bonding the first and second metallic layers; - decoupling the first substrate (102) from the chip and the encapsulation material; - creating at least one redistribution layer (121) electrically coupled to the electrical interconnection face;- realization of electrical interconnection elements (122) on the redistribution layer such that the electrical interconnection elements are electrically coupled to the chip by the redistribution layer.;