System-in-Packages With Through-Vias and Dummy Substrates
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Solution Overview
Problem
Current system-in-package technologies face challenges in manufacturing complexity and structural reliability due to increasing electrical connections and lead counts in high-density IC chips, particularly in achieving efficient inter-chip and intra-chip interconnections.
Innovation Solution
The system-in-package design incorporates multi-layer chips and dummy substrates with through vias and metal plugs for electrical interconnections, allowing for blind or complete through-chip interconnections and the use of metal interconnects between chips and external circuits, facilitating easier manufacturing and improved uniformity in silicon thinning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional WLP technology is used to package IC chips at wafer level, then production efficiency and cost are improved, but manufacturing complexity and structural reliability deteriorate due to increasing electrical connections and lead counts
Solution Approach 1:
The patent divides the chip structure into multiple layers with through-vias creating separate connection paths. Each layer can be processed and connected independently, segmenting the complex interconnection task into manageable units that reduce overall manufacturing complexity while maintaining high production efficiency
Solution Approach 2:
The patent transitions from planar 2D interconnections to 3D vertical interconnections through through-vias. This dimensional change allows multiple electrical connections to be stacked vertically, reducing the footprint and lead count on each layer while managing the complexity of increasing electrical connections
2Productivity
If traditional WLP technology is used to package IC chips at wafer level, then production efficiency and cost are improved, but structural reliability deteriorates due to increasing lead counts
Solution Approach 1:
The patent applies different material properties and structural characteristics to different regions of the chip package. Through-vias in high-stress areas use reinforced structures or different filling materials, while other areas use standard interconnections. This localized optimization maintains structural reliability across the entire package while preserving production efficiency
Solution Approach 2:
The patent employs composite material structures in the through-via construction, combining multiple metal layers, barrier layers, and dielectric materials. This composite approach enhances the mechanical strength and electrical reliability of each connection point, thereby improving overall structural reliability without compromising the high-throughput WLP manufacturing process
3Adaptability or versatility
If increasing electrical connections are made in high-density IC chips, then device functionality is improved, but manufacturing complexity increases
Solution Approach 1:
The patent implements nested interconnection structures where through-vias contain multiple conductive layers and intermediate structures within them. This nesting allows multiple electrical connections to be packed into a single vertical pathway, increasing device functionality while reducing the overall manufacturing complexity by consolidating connection points
Solution Approach 2:
The patent introduces intermediary structures such as redistribution layers and via fill materials that mediate between different interconnection levels. These intermediaries simplify the manufacturing process by providing standardized interfaces between layers, making it easier to manage increasing electrical connections without proportionally increasing manufacturing complexity
Data Source
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AI summary
System-in packages, or multichip modules, are described which can include multi-layer chips and multi-layer dummy substrates over a carrier, multiple through vias blindly or completely through the multi-layer chips and completely through the multi-layer dummy substrates, multiple metal plugs in the through vias, and multiple metal interconnects, connected to the metal plugs, between the multi-layer chips. The multi-layer chips can be connected to each other or to an external circuit or structure, such as mother board, ball grid array (BGA) substrate, printed circuit board, metal substrate, glass substrate, or ceramic substrate, through the metal plugs and the metal interconnects.