SiP Underfill Contamination Prevention via Bond Wire Studs
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Solution Overview
Problem
Conventional system-in-package (SiP) packaging faces issues with bond wire contamination and yield loss due to underfill material overflowing onto bond pads, limiting design flexibility and leading to mechanical instability and electrical failures, especially in reduced dimension semiconductor packages.
Innovation Solution
The use of bond wire studs on the substrate surface, which are formed before mounting the chip, allows underfill material to encapsulate solder bumps without overflowing onto the studs, enabling proper wire bonding and reducing yield loss, while allowing for closer chip-to-pad spacing and more design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If underfill material is dispensed to provide mechanical reinforcement, then reliability is improved, but bond wire contamination occurs and yield loss increases
Solution Approach 1:
The substrate surface is segmented into distinct functional zones: a first region with bond pads for wire bonding and a second region with solder bumps for chip mounting. This spatial segmentation prevents underfill material dispensed in the second region from contaminating bond pads in the first region, thereby maintaining both mechanical reinforcement and electrical connection integrity
Solution Approach 2:
A barrier layer is introduced as an intermediary between the bond pads and the underfill material. This barrier layer prevents direct contact between the underfill resin and bond pads, eliminating contamination while allowing the underfill to provide mechanical reinforcement to the package structure
2Object-affected harmful factors
If minimum distance between chip edge and bond pad is increased to avoid underfill overflow, then contamination is reduced, but design flexibility is limited and package dimensions cannot be reduced
Solution Approach 1:
The substrate surface is divided into functionally distinct regions: a first region dedicated to wire bonding with bond pads, and a second region for chip mounting with solder bumps. This segmentation allows the chip to be positioned closer to bond pads than conventional designs require, since underfill dispensed in the second region cannot overflow into the first region, thereby enabling reduced package dimensions while maintaining design flexibility
Solution Approach 2:
A barrier layer is positioned between the bond pads and the underfill material, acting as a mediator that prevents underfill overflow onto bond pads. This allows designers to place chips closer to bond pads without contamination risk, increasing design flexibility and enabling compact package designs
3Reliability
If underfill material is dispensed before wire bonding, then mechanical reinforcement is provided, but bond wire contamination and yield loss occur
Solution Approach 1:
The substrate is divided into spatially separated regions: bond pads in a first region for wire bonding and solder bumps in a second region for underfill dispensing. This segmentation allows underfill to be dispensed before wire bonding without contamination, as the underfill is confined to the second region while wire bonding occurs in the first region, thereby maintaining both mechanical reinforcement and high yield
Solution Approach 2:
A barrier layer is introduced as a mediator between the underfill material and bond pads, preventing contamination during the underfill dispensing process. This allows the underfill to be applied before wire bonding to provide mechanical reinforcement, while the barrier layer protects bond pads from contamination, eliminating yield loss
Data Source
AI summary
A system-in-package (SiP) package is provided. In one embodiment, the SiP package comprises a substrate having a first surface and a second surface opposite the first surface, the substrate having a set of bond wire studs on bond pads formed on the second surface thereof; a first semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the first semiconductor chip is mounted to the second surface of the substrate by means of solder bumps; an underfill material disposed between the first semiconductor chip and the substrate, encapsulating the solder bumps; a second semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the second semiconductor chip is mounted to the second surface of the first semiconductor chip; and a set of bond wires electrically coupled from the second semiconductor chip to the set of bond wire studs on the substrate.


