SiP Vertical Stacking for Reduced Footprint and Parasitic Capacitance
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Solution Overview
Problem
Traditional multi-chip modules (MCMs) face challenges in miniaturization due to large system-on-a-chip (SoC) and crystal components, leading to increased parasitic capacitance and footprint, which hinders the development of smaller wireless devices with greater functionality.
Innovation Solution
The implementation of a system-in-a-package (SiP) with vertical integration of SoCs and discrete components, including a crystal, using a substrate to reduce footprint and parasitic capacitance by stacking components, thereby minimizing trace length and coupling between sensitive paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional MCM horizontal integration is used, then component interconnections are established, but package footprint and parasitic capacitance increase
Solution Approach 1:
The patent transitions from horizontal integration (2D plane) to vertical integration (3D stacking), moving components from the x-y plane to the z-dimension. This dimensional change eliminates the need for extensive trace routing on the substrate, reducing parasitic capacitance while maintaining electrical interconnections through vertical vias and stacked component architecture.
2Reliability
If crystal and SoC are placed horizontally on substrate, then clocking and processing functions are provided, but parasitic capacitance increases affecting crystal oscillation
Solution Approach 1:
By stacking the crystal vertically above the SoC rather than placing it horizontally adjacent to the SoC, the patent minimizes the trace length and reduces parasitic capacitance in the clock signal path. This vertical arrangement improves crystal oscillation reliability by reducing the harmful capacitive effects that would otherwise interfere with the oscillation startup.
3Adaptability or versatility
If more components are integrated horizontally, then device functionality increases, but package size increases
Solution Approach 1:
The patent enables higher component integration density by utilizing the vertical z-dimension for stacking multiple components (SoC, crystal, filters, LNA, PA) rather than spreading them out horizontally. This allows advanced wireless functionality with multiple RF chains and filtering stages to be achieved within a compact package footprint, effectively decoupling functionality from package area.
4Reliability
If long crystal routing paths are used, then crystal connections are established, but parasitic capacitance adversely affects oscillation startup
Solution Approach 1:
The vertical stacking architecture reduces crystal trace length by connecting the crystal directly above the SoC through short vertical vias rather than requiring long horizontal traces across the substrate. This dimensional repositioning minimizes the trace length to the essential minimum, reducing parasitic capacitance and ensuring reliable oscillation startup.
Data Source
AI summary
A packaged module for use in a wireless communication device has a substrate supporting an integrated circuit die that includes at least a microprocessor and radio frequency receiver circuitry and a stacked filter assembly configured as a filter circuit that is in communication with the radio frequency receiver circuitry. The stacked filter assembly includes a plurality of passive components, where each passive component is packaged as a surface mount device. At least one passive component is in direct communication with the substrate and at least another passive component is supported above the substrate by the at least one passive component that is in the direct communication with the substrate.