Site-Level Overlay Correction for Semiconductor Lithography

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Solution Overview

Problem

The challenge in semiconductor fabrication is misalignment between patterns in different layers, leading to connection failures and increased lithography rework due to process variability and tight specifications at shrinking technology nodes.

Innovation Solution

A method involving a computing device to perform exposure with correction parameters, collect overlay data, estimate optimal parameters, and apply them to align overlays, using site-level run-to-run control to model and correct registration errors, thereby reducing misalignment and rework.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional lithography processes are used without correction parameters, then the fabrication process is simpler and faster, but overlay misalignment occurs causing connection failures and reduced yield

Engineering Contradiction:

Improveoverlay alignment accuracyVSAvoidlithography process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The system performs preliminary measurements on a first wafer to determine registration errors before actual production. Correction parameters are calculated in advance and applied to subsequent wafers, preventing overlay misalignment before it occurs rather than detecting and correcting it after the fact

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system implements a feedback loop where overlay measurements from processed wafers are continuously fed back to update correction parameters. The controller uses measured registration errors to generate decorrections that are applied to subsequent lithography exposures, creating a closed-loop control system that progressively improves overlay accuracy

Inventive Principle:

Principle #23Feedback

2Manufacturing precision

If correction parameters are applied to all wafers uniformly, then overlay alignment is improved, but the system cannot account for site-specific variations in registration errors

Engineering Contradiction:

Improvesite-level overlay precisionVSAvoidparameter estimation complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The system transitions from uniform correction parameters applied to entire wafers to site-level correction parameters. Each site on the wafer receives customized correction values based on local registration error measurements, allowing precise correction of position, magnification, and rotation specific to each region rather than applying a blanket correction

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The wafer is divided into multiple sites, and the correction process is segmented into site-specific operations. The system estimates optimal parameters for each site individually and applies differentiated corrections, breaking down the complex problem of wafer-level overlay control into manageable site-level components

Inventive Principle:

Principle #1Segmentation

3Reliability

If aggressive correction parameters are applied to maximize overlay alignment, then misalignment is reduced, but the corrections may amplify measurement noise and create instability

Engineering Contradiction:

Improveoverlay alignment reliabilityVSAvoidcorrection parameter stability

Core Design Contradiction:

ReliabilityVSStability of the object's composition

Solution Approach 1:

The system applies damping factors to correction parameters before they are applied to wafers. This pre-cushioning approach reduces the impact of measurement noise and prevents over-correction by scaling down aggressive correction values, ensuring stable and gradual improvement of overlay alignment without amplifying errors

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The system uses damping to apply partial corrections rather than full corrections based on measured errors. By applying only a portion of the calculated correction (damped correction), the system avoids excessive action that could amplify noise and creates a more stable, gradual convergence toward optimal overlay alignment

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS11036912B2Overlay optimization

Publication Date: 2021.06.15 KLA CORP

AI summary

The present disclosure generally relates to semiconductor structures and, more particularly, to overlay optimization and methods of manufacture. The method includes performing, by a computing device, an exposure with a correction parameter to a first wafer; performing, by the computing device, a decorrection of the correction parameter; collecting, by the computing device, overlay data in response to the exposure and the decorrection; estimating, by the computing device, an optimal parameter from the overlay data; and applying, by the computing device, the optimal parameter to a second wafer to align an overlay in the second wafer.