Substrate Integrated Waveguide Via Formation for GaN Packaging
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Solution Overview
Problem
Existing silicon manufacturing processes for substrate integrated waveguides (SIWs) in the millimeter wave (mmW) band face challenges in achieving precise dimensions and high-volume production efficiency, particularly for 5G communication devices, and struggle to integrate with gallium nitride (GaN) die packaging.
Innovation Solution
A method involving a high resistivity silicon substrate with a gold layer on the top surface and a copper layer on the bottom surface and interior via surfaces, using a lift-off process and through-silicon-via etching, to form parallel rows of vias that define the waveguide dimensions, ensuring compatibility with GaN die packaging and high Q resonators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional through glass vias or printed circuit board vias are used, then manufacturing is simpler, but manufacturing precision and high-volume production efficiency are insufficient for mmW band SIWs
Solution Approach 1:
The patent changes the substrate material parameter from traditional glass or printed circuit board to silicon substrate, enabling precise via dimensions (e.g., 10-50 micrometer diameter) required for mmW band operation. The silicon substrate allows for controlled via formation through standard semiconductor processing techniques, achieving the necessary dimensional precision while maintaining compatibility with high-volume production methodologies.
2Manufacturing precision
If precise via dimensions are achieved through advanced etching, then manufacturing precision improves, but production efficiency and high-volume manufacturing capability deteriorate
Solution Approach 1:
The patent segments the via formation process into discrete, repeatable steps including photoresist coating, patterning, and etching. This segmentation allows each step to be optimized independently and enables parallel processing of multiple wafers simultaneously, thereby achieving both precise via spacing (e.g., 250 micrometer pitch) and high-volume production efficiency through standardized semiconductor manufacturing workflows.
3Reliability
If silicon substrate with lift-off process and through-silicon-via etching is used, then manufacturing precision and GaN die packaging compatibility improve, but device complexity increases
Solution Approach 1:
The patent employs a multi-functional manufacturing approach where the silicon substrate serves multiple purposes: it provides the mechanical support structure, the dielectric medium for mmW signal propagation, and the platform for via formation. The lift-off process and through-silicon-via etching are integrated into a unified sequence that simultaneously achieves precise via formation, gold layer deposition, and compatibility with GaN die packaging standards, thereby managing complexity through functional integration rather than addition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the production of high-Q SIWs with precise dimensions suitable for mmW frequencies, compatible with GaN die packaging, and suitable for high-volume production, overcoming limitations of traditional processes such as through glass vias and printed circuit board vias.
Implementation Method 1
a gold layer is disposed on a top surface of a substrate (e.g., high resistivity silicon substrate) using a lift-off process
Implementation Method 2
two parallel rows of equal (or substantially equal) spaced vias that are separated by a width of the substrate integrated waveguide are formed in the silicon substrate using a through-silicon-via etching process
Implementation Method 3
a copper layer is disposed on the bottom side of the silicon substrate and on interior surfaces of each via
Data Source
AI summary
A method for manufacturing a substrate integrated waveguide for a millimeter wave signal is disclosed. In the method, a gold layer is disposed on a top surface of the silicon substrate using a lift-off process. Next, two parallel rows of substantially equal spaced vias are formed in the silicon substrate using a through-silicon-via etching process. Then, a copper layer is disposed on the bottom side of the silicon substrate and on interior surfaces of each via. The separation between the copper layer and the gold layer define a height of the substrate integrated waveguide, while the separation between the two parallel rows of substantially equal spaced vias define a width of the substrate integrated waveguide. In some implementations the length of the substrate defines a length of the substrate integrated waveguide, and the length, width, and height define a resonator that is resonant at a millimeter wave frequency.