Six-Phase Charge Pump Clocking for Parasitic Charge Sharing
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Solution Overview
Problem
High output voltage charge pump circuits suffer from poor power and area efficiency due to charge loss in parasitic capacitors and unpredictable switch operations caused by imperfect clock signals.
Innovation Solution
A charge pump circuit with a six-phase clock and a gate boosting charge pump, which includes a Boolean logic circuit for generating clock signals and a tri-state buffer circuit for enabling charge-sharing operations between parasitic capacitors, thereby reducing reversion losses and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If charge pump circuits use higher output voltage, then power source capability is improved, but power efficiency deteriorates due to charge loss in parasitic capacitors
Solution Approach 1:
The patent implements a charge recovery mechanism where charge from the parasitic capacitor is transferred to the pump capacitor during specific clock phases. The bottom plate of the parasitic capacitor is connected to the top plate of the pump capacitor through switch S3, allowing the stored charge to be recovered and utilized rather than discarded, thereby reducing overall charge loss in the system.
Solution Approach 2:
The patent introduces a tri-state buffer circuit as an intermediary component that manages the interaction between clock signals and the charge pump circuit. This buffer circuit controls the timing and state of clock signals, enabling precise control over switch operations and facilitating the charge transfer mechanism between parasitic and pump capacitors, thereby improving power efficiency.
2Ease of operation
If clock signals are used to control switches, then circuit operation is improved, but unpredictability during voltage transitions increases causing reverse currents
Solution Approach 1:
The patent employs a tri-state buffer circuit that generates clock signals with controlled timing characteristics. The buffer circuit prepares and conditions the clock signals before they reach the switches, ensuring that voltage transitions occur at predictable times and in a controlled manner, thereby preventing unpredictable switch behavior and reverse currents during transitions.
3Productivity
If charge-sharing operation is implemented, then current efficiency is improved, but area increases marginally
Solution Approach 1:
The patent designs the charge pump circuit where the parasitic capacitor serves multiple functions: it acts as both a parasitic element inherent to the circuit and as an active charge storage element that contributes to the charge pumping operation. By utilizing the parasitic capacitor's charge through the tri-state buffer controlled mechanism, the circuit achieves improved current efficiency without requiring additional dedicated capacitors, thus minimizing area increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances the power efficiency of high output voltage, low output current charge pumps without increasing the area, by minimizing charge loss and reversion losses through effective charge-sharing and clock signal management.
Implementation Method 1
The gate boosting charge pump includes a plurality of pump capacitors configured to store an amount of charge
Implementation Method 2
enabling a charge-sharing operation to share the stored amount of charges between a plurality of parasitic capacitors
Data Source
AI summary
The present disclosure relates to a charge pump circuit with a six-phase clock. The charge pump circuit comprises a six-phase clock circuit and a gate boosting charge pump configured to receive a plurality of clock signals from the six-phase clock circuit. The six-phase clock circuit includes provides a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a fifth clock signal, and a sixth clock signal. The gate boosting charge pump is configured to enable a charge-sharing operation to share the stored amount of charges between a plurality of parasitic capacitors. The six-phase clock circuit is configured to provide a dead time between each of the first, second, third, fourth, fifth and sixth clock.