Size-Based Geometry Rendering with Hierarchical Tile Control Lists
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Solution Overview
Problem
Tile-based graphics processing systems face inefficiencies in memory bandwidth and footprint due to the replication of large primitives in multiple control lists, particularly in applications with a small number of large primitives, leading to increased data transfer and memory usage.
Innovation Solution
Implement hierarchical tiling by subdividing the rendering space into multiple levels of regions, using first and second control lists based on the spatial coverage of geometry within these regions, reducing redundant data storage by adding large primitives to higher-level lists and smaller ones to lower-level lists.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large primitives are added to multiple control lists in tile-based rendering, then rendering coverage is improved, but memory bandwidth and footprint increase due to redundant data storage
Solution Approach 1:
The patent segments the rendering space into multiple hierarchical levels of regions (e.g., tiles, macro tiles, and display targets), each with its own control list. This segmentation allows different levels to manage geometry at appropriate granularities, reducing redundancy by avoiding duplication of large primitives across all control lists while ensuring complete coverage through the hierarchical structure.
Solution Approach 2:
The patent implements a hierarchical control list system where smaller control lists are nested within larger ones. Each region's control list contains references to primitives, and larger regions' control lists aggregate these references. This nesting enables efficient memory usage by allowing a single primitive to be referenced at multiple hierarchical levels without physical duplication, thus reducing overall memory footprint while maintaining rendering coverage.
2Reliability
If large primitives are replicated in multiple control lists, then geometry coverage is improved, but data transfer between memory and chip increases
Solution Approach 1:
The patent performs preliminary classification of primitives during the geometry processing phase, identifying which primitives are large and should be added to multiple control lists at different hierarchical levels. This preliminary action optimizes the control list structure before rendering, ensuring that large primitives are efficiently distributed across the hierarchical control list system, thereby reducing redundant data transfers during the actual rendering process.
3Quantity of substance
If hierarchical tiling is implemented with multiple levels of regions, then memory usage is optimized, but device complexity increases
Solution Approach 1:
The patent implements a universal control list data structure that can function at multiple hierarchical levels. The same control list mechanism is used for tiles, macro tiles, and display targets, with the only difference being the scope and granularity of regions they manage. This universality simplifies the system by reusing the same control list logic across all levels, reducing the actual complexity increase despite the hierarchical structure.
Data Source
AI summary
Graphics processing systems render items of geometry using a rendering space subdivided into a plurality of first regions. The items of geometry are stored in data blocks having a respective block ID. The items of geometry are rendered within a second region of a plurality of second regions using a first control list for the first region of which the second region is a part, and a second control list for the second region, each control list comprising entries associated with respective items of geometry, each of the entries comprising a block ID associated with a data block. The items of geometry are rendered within the second region by choosing from the first control list and the second list, the entry comprising the lowest block ID which has not previously been chosen, and fetching items of geometry from the data block associated with the block ID of the chosen entry.