SJ-MOSFET Buffer Layer Doping for Cosmic Ray Tolerance
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Solution Overview
Problem
Conventional SJ-MOSFETs face challenges in maintaining charge balance and cosmic ray tolerance due to rapid depletion layer spreading, leading to electric field concentration and potential avalanche breakdown at the interface between the n-type buffer layer and the n++-type drain layer, which can result in device destruction.
Innovation Solution
The semiconductor device incorporates a multistage epitaxial growth structure for the n+-type buffer layer with an impurity concentration distribution that increases step-wise towards the n++-type drain layer, suppressing the depletion layer spreading and electric field concentration, thereby enhancing cosmic ray tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the impurity concentration of the n-type buffer layer is increased to suppress depletion layer spreading, then cosmic ray tolerance is improved, but the charge balance between n-type and p-type column regions deteriorates
Solution Approach 1:
The n-type buffer layer is divided into multiple layers with different impurity concentrations. The first n-type buffer layer has a higher impurity concentration to suppress depletion layer spreading and improve cosmic ray tolerance, while the second n-type buffer layer has a lower impurity concentration to maintain charge balance with the p-type column regions.
Solution Approach 2:
Different regions of the n-type buffer layer are assigned different impurity concentrations based on their functional requirements. The region closer to the parallel pn layer has lower impurity concentration for charge balance, while the region closer to the n++-type drain layer has higher impurity concentration for depletion layer suppression.
2Reliability
If the thickness of the n-type buffer layer is increased to prevent depletion layer reaching the n++-type drain layer, then breakdown voltage is maintained, but the device size and on-resistance deteriorate
Solution Approach 1:
Instead of increasing the thickness of the n-type buffer layer, the invention changes the impurity concentration parameter. By creating a gradient of impurity concentrations within a compact thickness, the depletion layer is suppressed without increasing device size, maintaining breakdown voltage while minimizing dimensional growth.
3Reliability
If the impurity concentration distribution is optimized to suppress electric field concentration, then avalanche breakdown is prevented, but manufacturing complexity increases
Solution Approach 1:
The continuous impurity concentration gradient is segmented into discrete layers with step-wise different concentrations. This segmentation achieves the desired electric field distribution and avalanche breakdown resistance while simplifying the manufacturing process compared to creating a perfectly continuous gradient.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively prevents rapid depletion layer suppression and electric field concentration, reducing the risk of avalanche breakdown and enhancing cosmic ray tolerance without increasing the thickness of the n+-type buffer layer, thus improving the reliability of the semiconductor device.
Implementation Method 1
The semiconductor device incorporates a multistage epitaxial growth structure for the n+-type buffer layer with an impurity concentration distribution that increases step-wise towards the n++-type drain layer
Implementation Method 2
Conventional SJ-MOSFETs face challenges in maintaining charge balance and cosmic ray tolerance due to rapid depletion layer spreading, leading to electric field concentration and potential avalanche breakdown at the interface between the n-type buffer layer and the n++-type drain layer
Data Source
AI summary
A drift layer has a SJ structure with a parallel pn layer; an n+-type buffer layer is between the parallel pn layer and an n++-type drain layer. An impurity concentration of the n+-type buffer layer is adjusted to be at least equal to that of n-type column regions of the parallel pn layer, to be relatively low in a portion facing the parallel pn layer and approach the impurity concentration of the n-type column regions, and to increase closer to the n++-type drain layer. The impurity concentration of the n+-type buffer layer is adjusted so that an impurity concentration difference between the n+-type buffer layer and the n++-type drain layer near the border between the n+-type buffer layer and the n++-type drain layer is as small as possible. An impurity concentration distribution of the n+-type buffer layer is formed by stacking n+-type buffer layers in descending order of impurity concentration from the n++-type drain layer.