Small Pitch Super Junction MOSFET Pillar Optimization
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Solution Overview
Problem
Small pitch super junction (SJ) power MOSFET devices face challenges such as reduced breakdown tolerance, fragility, and lower MOSFET saturation current due to depletion of narrow pillars, requiring improved manufacturing processes and robustness to maintain low specific on resistance.
Innovation Solution
The semiconductor device features a drift region with alternating P and N pillars of varying widths and doping levels, forming a super junction structure that separates SJ epitaxial wafer preparation from MOSFET fabrication, allowing for common wafer use across different product sizes, enhancing breakdown voltage and robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If small pitch SJ MOSFET devices are used to reduce specific on resistance, then on resistance decreases, but breakdown tolerance reduces and manufacturing window narrows
Solution Approach 1:
The patent applies parameter changes by varying the doping concentrations and geometric dimensions of P and N pillars across different regions of the device. Specifically, the drift region contains P pillars with first doping concentrations and N pillars with second doping concentrations, where these parameters are optimized to achieve charge balance while maintaining breakdown tolerance. The pillar widths and spacing are carefully controlled to reduce on-resistance without compromising reliability.
Solution Approach 2:
The patent implements local quality by creating spatially varying properties within the drift region. Different regions have different P and N pillar configurations, with varying doping concentrations and geometries. This allows the device to have low on-resistance in active regions while maintaining higher breakdown tolerance in other regions, effectively resolving the contradiction between low resistance and high breakdown capability.
2Manufacturing precision
If small pitch SJ MOSFET devices are used to reduce specific on resistance, then on resistance decreases, but device fragility increases
Solution Approach 1:
The patent employs beforehand cushioning by designing the drift region with carefully balanced P and N pillars that provide structural and electrical stability. The charge-balanced configuration creates inherent mechanical and electrical robustness that cushions against device fragility. The specific arrangement and doping of pillars provide a buffer that prevents catastrophic failure while maintaining low on-resistance characteristics.
3Manufacturing precision
If small pitch SJ MOSFET devices are used to reduce specific on resistance, then on resistance decreases, but MOSFET saturation current reduces due to pillar depletion
Solution Approach 1:
The patent uses parameter changes by optimizing the doping concentrations of P and N pillars to achieve charge balance while maintaining adequate carrier supply. The doping levels are specifically tuned so that pillars remain partially depleted for low resistance but have sufficient charge to maintain saturation current. The geometric parameters of pillars are also optimized to balance these competing requirements.
Solution Approach 2:
The patent applies local quality by creating regions with different pillar characteristics. Some regions have pillars optimized for low resistance with specific depletion characteristics, while other regions maintain pillars with higher charge density to ensure adequate saturation current. This spatial variation in pillar quality allows the device to achieve both low on-resistance and maintained saturation current capability.
Data Source
AI summary
The present invention provides semiconductor devices with super junction drift regions that are capable of blocking voltage. A super junction drift region is an epitaxial semiconductor layer located between a top electrode and a bottom electrode of the semiconductor device. The super junction drift region includes a plurality of pillars having P type conductivity, formed in the super junction drift region, which are surrounded by an N type material of the super junction drift region.