SJ-MOSFET Trap Level Design for Reverse Recovery Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional SJ-MOSFETs experience a large reverse recovery current and self-turn-on effect when used in inverter circuits for motor drives, leading to excessive switching losses and inefficiencies, particularly in low power load operations.
Innovation Solution
A semiconductor device with a specific structure including a first conductivity type drain layer, drift layer, base regions, source regions, gate insulating layer, and trap level forming regions, optimized to reduce reverse recovery time and prevent self-turn-on by adjusting the ratio of gate-source to gate-drain capacitance, thereby minimizing on-resistance and switching losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If SJ-MOSFET is used to reduce on-resistance and switching losses, then energy efficiency is improved, but reverse recovery current increases causing self-turn-on effect
Solution Approach 1:
The patent applies local quality by creating trap levels at specific locations within the drift layer (at depths of 0.05-0.20 times the drift layer thickness) to selectively affect carrier behavior. This localized modification reduces reverse recovery current in the body diode without compromising the overall low on-resistance characteristic of the SJ-MOSFET, thereby resolving the contradiction between energy efficiency and harmful reverse recovery effects
Solution Approach 2:
The patent changes physical parameters by introducing trap levels with specific energy states (0.5-1.5 eV below the conduction band) and controlling their concentration (1×10^15 to 1×10^17 atoms/cm³). These parameter changes modify the carrier lifetime and distribution, reducing reverse recovery current while maintaining the super junction structure's low on-resistance property
2Loss of time
If trap level is formed to reduce reverse recovery current, then reverse recovery time is reduced, but self-turn-on effect occurs in miniaturized structures
Solution Approach 1:
The patent carefully controls the trap level concentration parameter (1×10^15 to 1×10^17 atoms/cm³) and depth distribution to achieve optimal reverse recovery time reduction while preventing excessive carrier trapping that could cause self-turn-on. The specific parameter range balances reverse recovery performance with device reliability in miniaturized structures
Solution Approach 2:
By concentrating trap levels at specific depths (0.05-0.20 times drift layer thickness) rather than uniformly distributing them, the patent achieves localized carrier management that reduces reverse recovery time without creating the widespread carrier depletion that would lead to self-turn-on effects in miniaturized devices
3Ease of manufacture
If conventional SJ-MOSFET structure is used, then manufacturing is simplified, but additional circuitry is needed to prevent self-turn-on
Solution Approach 1:
The patent merges the function of reverse recovery current reduction directly into the MOSFET's drift layer by incorporating trap levels during manufacturing. This integration eliminates the need for external circuitry or additional components to prevent self-turn-on, maintaining manufacturing simplicity while reducing overall system complexity
Solution Approach 2:
The trap level structure enables the MOSFET to self-regulate carrier behavior during reverse recovery, automatically preventing self-turn-on effects without requiring external control circuits or additional devices. The structure serves its own protection function, maintaining ease of manufacture while reducing device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device effectively reduces reverse recovery time and prevents self-turn-on effects, enhancing energy efficiency and reducing losses in inverter circuits, especially in low power load operations, without the need for additional circuitry.
Implementation Method 1
there has been proposed an SJ-MOSFET which is capable of significantly reducing a reverse recovery current Irr by forming a local trap level in a semiconductor and controlling lifetime of minor carriers
Implementation Method 2
a gate insulating layer covering the channel region; a gate electrode which is located on the gate insulating layer and faces the channel region
Implementation Method 3
an SJ-MOSFET having a super junction structure (hereinafter sometimes referred to as an "SJ-MOSFET") can realize a higher breakdown voltage (e.g., a drain-source voltage of 500 volts or higher) with a lower on-resistance
Data Source
AI summary
A semiconductor device includes a conductivity type drain layer, a conductivity type drift layer, conductivity type base regions located in an upper surface of the drift layer, a conductivity type source region which is disposed inside each of the base regions and is spaced apart from the periphery of the base region, and a channel region is formed between the source region and the periphery of the base region. The semiconductor device further includes a gate insulating layer covering the channel region, a gate electrode which is located on the gate insulating layer and faces the channel region, a plurality of conductivity type column regions, each extends from the plurality of base regions to the drain layer in the drift layer, a trap level forming region in the drift layer, a drain electrode electrically connected to the drain layer, and a source electrode electrically connected to the source region.