SKEIN256 Instruction Set for 128-bit Processor Security
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Solution Overview
Problem
Current instruction processing apparatuses face inefficiencies in executing SKEIN256, SKEIN512, and SKEIN1024 secure hashing algorithms, particularly in performing multiple rounds of MIX-PERMUTE operations, which are crucial for cryptographic security but require optimized pipeline and register management.
Innovation Solution
The development of specialized instruction sets and execution units within processors that enable efficient execution of SKEIN operations through SIMD instructions, utilizing 128-bit registers and specific instruction formats like AVX, allowing for multiple rounds of SKEIN MIX-PERMUTE operations with reduced cycles and optimized operand management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple rounds of MIX-PERMUTE operations are executed for SKEIN algorithms, then cryptographic security is improved, but processing time and computational complexity increase
Solution Approach 1:
The patent divides the SKEIN algorithm into distinct functional modules: MIX function, PERMUTE function, and sub-key addition. Each module is implemented as a separate execution unit that can operate independently or in parallel, allowing the multiple rounds of operations to be segmented and executed more efficiently across different pipeline stages.
Solution Approach 2:
The patent combines multiple MIX functions and PERMUTE operations into a unified execution pipeline that processes multiple rounds simultaneously. By merging these operations into a single integrated pipeline with shared registers and memory structures, the system reduces the total cycle count while maintaining the required security rounds.
2Adaptability or versatility
If multiple MIX functions are executed per round for SKEIN256/512/1024, then algorithm completeness is improved, but device complexity increases
Solution Approach 1:
The patent designs a universal execution unit that can perform multiple MIX functions and PERMUTE operations using the same hardware resources. The execution unit is configured with multiple registers and memory access paths that can be dynamically allocated and reassigned across different rounds, eliminating the need for separate dedicated circuits for each function.
Solution Approach 2:
The patent implements dynamic register allocation and memory access patterns that adapt to the current round of operations. The execution unit can dynamically switch between different register pairs and memory addresses based on the PERMUTE table requirements, allowing a single static hardware structure to handle variable algorithm requirements without increasing complexity.
3Productivity
If 128-bit registers and SIMD instructions are used for SKEIN operations, then processing efficiency is improved, but instruction set complexity increases
Solution Approach 1:
The patent uses 128-bit register copies and SIMD instruction templates that can be replicated across multiple execution units. By copying the same register structure and instruction format across all execution units, the system achieves parallel processing efficiency while maintaining instruction simplicity through template reuse rather than creating unique complex instructions for each function.
Data Source
AI summary
According to one embodiment, a processor includes an instruction decoder to receive a first instruction to perform first SKEIN256 MIX-PERMUTE operations, the first instruction having a first operand associated with a first storage location to store a plurality of odd words, a second operand associated with a second storage location to store a plurality of even words, and a third operand. The processor further includes a first execution unit coupled to the instruction decoder, in response to the first instruction, to perform multiple rounds of the first SKEIN256 MIX-PERMUTE operations based on the odd words and even words using a first rotate value obtained from a third storage location indicated by the third operand, and to store new odd words in the first storage location indicated by the first operand.