Skew Cell Layout With Cut Poly Gates for Low-Leakage Sizing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Standard cell architectures face challenges in incorporating L-shaped diffusion regions due to increased costs and leakage effects, limiting the ability to provide skewed sizing for PMOS and NMOS devices, which complicates fabrication and reduces efficiency in logic circuits.

Innovation Solution

The implementation of a novel skew cell layout architecture that allows for double-height or quad-height skew cells by positioning P-type and N-type diffusion regions with cut poly-gate rails to create open spaces, enabling rise and fall skewed designs that improve timing and reduce leakage, suitable for various circuit applications including IoT and automotive systems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If L-shaped diffusion regions are used for skewed sizing, then PMOS and NMOS device sizing flexibility is improved, but fabrication cost increases due to additional mask layers

Engineering Contradiction:
Improveskewed sizing flexibilityVSAvoidfabrication cost
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The cell is divided into two separate height sections: a first height section containing PMOS devices and a second height section containing NMOS devices. This segmentation allows each section to be independently sized and optimized, achieving skewed sizing without requiring L-shaped diffusion regions that would add fabrication complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar 2D layout constraints to 3D vertical stacking by utilizing different cell heights for PMOS and NMOS sections. This dimensional change enables skewed sizing while maintaining standard fabrication processes, as the height differentiation is achieved through vertical stacking rather than complex lateral diffusion patterns

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If L-shaped diffusion regions are used for skewed sizing, then device sizing flexibility is improved, but leakage effects increase

Engineering Contradiction:
Improveskewed sizing flexibilityVSAvoidleakage effects
Core Design Contradiction:
Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

By segmenting the cell into separate PMOS and NMOS height sections with distinct active regions, the patent eliminates the need for L-shaped diffusion connections. Each transistor type has its own rectangular active region, preventing the leakage issues associated with L-shaped diffusions while maintaining skewed sizing capability through height differentiation

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses separate, complete active regions for PMOS and NMOS devices rather than sharing or connecting them through L-shaped structures. Each section is a self-contained copy of a standard cell section, eliminating the harmful L-shaped diffusion geometry that causes leakage while preserving the ability to size devices differently

Inventive Principle:
Principle #26Copying

3Productivity

If standard cell architecture is used, then fabrication efficiency is maintained, but skewed sizing for logic circuits is limited

Engineering Contradiction:
Improvefabrication efficiencyVSAvoidskewed sizing capability
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent introduces dynamic height allocation where the first height section and second height section can be independently configured to match the specific sizing requirements of PMOS and NMOS logic circuits. This dynamic adaptability allows standard fabrication processes to produce customized skewed cells without requiring new fabrication techniques, maintaining efficiency while enhancing versatility

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The dual-height cell structure serves multiple functions: it enables skewed sizing for different logic circuits, maintains compatibility with standard fabrication processes, and allows independent optimization of PMOS and NMOS sections. This multi-functionality achieves adaptability without sacrificing fabrication efficiency

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250015133A1Skew Cell Architecture
Publication Date: 2025.01.09 ARM LTD
  • US20250015133A1 patent drawing
  • US20250015133A1 patent drawing
  • US20250015133A1 patent drawing

AI summary

Various implementations described herein are directed to a device having a skew cell architecture with multiple diffusion regions including P-type diffusion regions disposed between N-type diffusion regions. The device may have power rails including a voltage supply rail disposed between ground rails. The device may have poly-gate rails disposed between the ground rails. The poly-gate rails may be cut to provide an open space between at least one N-type diffusion region and at least one P-type diffusion region.