Digital Skew Compensation for Clockless Bi-Directional Data Links

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Solution Overview

Problem

In modern data communication systems, especially in DDR and QDR systems, the need for high-frequency clocks complicates miniaturization due to increased power consumption and noise, and requires bi-directional communication without a built-in clock, necessitating effective bias and random delay compensation in sampling signals.

Innovation Solution

A digital communication system with a host that produces a clock signal and includes a skew compensation mechanism using a voting mechanism and training mechanism to adjust sampling timing, allowing the device to synchronize without a clock, utilizing at least three samples to detect skew and adjust sampling timing in real-time, and storing digital values for memory restoration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a high-frequency clock is included in the device to enable bi-directional communication, then communication capability is improved, but power consumption and noise increase

Engineering Contradiction:
Improvebi-directional communication capabilityVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent removes the clock generator from the device, extracting the timing function from the device itself and placing it in the host. The device only receives clock signals from the host and generates data at multiple rates without requiring its own high-frequency clock, thereby eliminating the power consumption and noise associated with on-device clock generation while maintaining bi-directional communication capability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The host acts as an intermediary that provides the clock signal to the device. The device relies on the host's clock signal to synchronize its operations, allowing the host to control timing for both directions of communication. This intermediary approach eliminates the need for the device to generate its own high-frequency clock while maintaining full bi-directional communication functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If a high-frequency clock is included in the device to enable bi-directional communication, then communication capability is improved, but device size increases

Engineering Contradiction:
Improvebi-directional communication capabilityVSAvoiddevice size
Core Design Contradiction:
Adaptability or versatilityVSVolume of moving object

Solution Approach 1:

The patent removes the clock generator from the device, extracting the timing function from the device itself and placing it in the host. The device only receives clock signals from the host and generates data at multiple rates without requiring its own high-frequency clock, thereby eliminating the power consumption and noise associated with on-device clock generation while maintaining bi-directional communication capability.

Inventive Principle:
Principle #2Taking out (Extraction)

3Device complexity

If sampling timing is not adjusted for skew, then device complexity is reduced, but synchronization accuracy deteriorates

Engineering Contradiction:
Improvesynchronization circuit complexityVSAvoidsampling timing accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent implements a feedback mechanism where the device monitors the timing relationship between the received clock signal and the data signal. A skew detection mechanism provides feedback about timing deviations, and a skew compensation mechanism adjusts the sampling timing accordingly. This feedback loop maintains synchronization accuracy without requiring complex hardware by using software-based adjustment.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent adjusts the sampling timing parameter dynamically based on detected skew conditions. Instead of using fixed sampling timing, the system modifies the sampling moment by introducing variable delays or advances to compensate for timing skew. This parameter adjustment approach maintains synchronization accuracy while keeping the overall system relatively simple.

Inventive Principle:
Principle #35Parameter changes

4Measurement precision

If multiple samples are used for skew detection, then synchronization accuracy is improved, but measurement time increases

Engineering Contradiction:
Improveskew detection accuracyVSAvoidtraining time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs skew detection and compensation during an initial training phase before normal data transmission begins. The system uses multiple samples during this preliminary training period to accurately determine the skew condition, then locks in the optimized sampling timing for subsequent operation. This preliminary action allows high-accuracy skew detection without impacting the speed of normal data transmission.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses multiple samples (more than the minimum required) during the training phase to achieve high accuracy in skew detection. By using excessive sampling during this limited training period, the system establishes robust timing compensation parameters that can then be maintained throughout operation without requiring continuous high-cost measurement, thus balancing accuracy with time efficiency.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS8024599B2Bias and random delay cancellation
Publication Date: 2011.09.20 WESTERN DIGITAL ISRAEL LTD
  • US8024599B2 patent drawing
  • US8024599B2 patent drawing
  • US8024599B2 patent drawing

AI summary

A system and method for digital communication wherein a host provides a host clock and a clockless device transmits to the host a bit stream synchronized according to the clock at a data rate that is an integer multiple of the clock rate. A training mechanism using training data detects time skew between host clock and bit stream, and a digital skew compensation mechanism compensates, substantially in real time, for the skew and for variations in the skew that may occur with the passage of time, in accordance with a vote among at least three samples of a bit of the bit stream, subsequent sampling being retarded or advanced if, respectively, an early or late sample is in disagreement with the vote. Preferably, the compensation value is selected from at least four possible compensation values, and can be stored in a memory to hasten subsequent restarts of the system.