Skew-Tolerant Multiplexer Circuit for Glitch-Free Burst Sampling

The patent replaces the local PLL clock mechanism with a differential RCK strobe-based clocking system. Instead of using phase-locked loop circuits to generate sampling clocks, the invention uses differential strobe signals derived from the memory interface clock, eliminating the jitter accumulation inherent in PLL-based systems while maintaining precise timing alignment through differential signaling.

The invention changes the fundamental parameter of clock generation from active PLL synthesis to passive differential strobe sampling. By transitioning from a system that actively generates and adjusts clock phases to one that passively samples data using differential strobes synchronized to the memory interface, the patent eliminates jitter accumulation while preserving timing precision.

The patent implements continuous VT drift tracking that operates without interruption during burst-to-burst transitions. The differential RCK strobe system maintains continuous synchronization by constantly monitoring and compensating for voltage threshold drift, ensuring that the clocking relationship remains valid across burst boundaries without requiring re-training sequences.

The system performs preliminary VT drift compensation continuously during operation, so that when burst-to-burst transitions occur, the timing alignment is already maintained. By proactively tracking and compensating for drift throughout the operational cycle rather than reactively correcting it during transitions, the patent eliminates re-training requirements.