Skewable Scan Cell Asymmetric Clock Adjustment
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Solution Overview
Problem
Existing integrated circuit (IC) scan cells face challenges in managing clock skew, which varies between normal and scan modes due to differences in path length, load, and on-chip variations, leading to inefficiencies in clock signal distribution and increased power consumption.
Innovation Solution
The introduction of skewable scan cells with asymmetric skew adjustments in both normal and scan modes, utilizing timing compensation units with clock buffers to balance tree latency and reduce the number of timing buffers, allowing for unbalanced tree latency in scan and normal modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If symmetric skew adjustment is used in scan cells, then the circuit structure is simple, but clock skew cannot be optimized for both normal and scan modes simultaneously
Solution Approach 1:
The patent applies asymmetry by introducing different skew adjustment mechanisms for normal mode and scan mode. Specifically, it uses a first skew adjustment unit for normal mode operation and a second skew adjustment unit for scan mode operation, allowing each mode to have optimized skew characteristics independent of the other. This resolves the contradiction by making the scan cell structure asymmetric rather than symmetric, enabling separate optimization for each operational mode.
2Reliability
If the number of timing buffers is increased to reduce clock skew, then clock distribution accuracy improves, but chip area and power consumption increase
Solution Approach 1:
The patent applies local quality by placing timing buffers strategically only where needed in the clock tree structure. Instead of uniformly distributing timing buffers throughout the entire clock network, the invention identifies specific locations where skew adjustment is necessary and places timing buffers locally at those positions. This selective placement achieves clock skew optimization while minimizing the total number of timing buffers required, thereby reducing chip area and power consumption.
3Productivity
If scan-shift frequency is increased to reduce test time, then testing efficiency improves, but IR-drop issues worsen
Solution Approach 1:
The patent applies preliminary action by performing skew optimization and timing analysis before finalizing the scan chain configuration and clock tree synthesis. By conducting static timing analysis and adjusting skew parameters in advance, the invention ensures that the clock tree is properly balanced for high-frequency operation. This preliminary optimization of the clock distribution network reduces voltage drops and IR-drop issues that would otherwise occur during high-frequency scan-shift operations, enabling higher test frequencies without excessive IR-drop problems.
Data Source
AI summary
A replacement method for scan cell of an integrated circuit (IC) is provided. A gate-level netlist of the IC is obtained. A place-and-route process is performed on the gate-level netlist to obtain a first netlist. A clock tree synthesis process is performed on the first netlist to obtain a second netlist. Static timing analysis is performed to analyze a plurality of first scan cells of the second netlist in normal mode and scan mode. The first scan cell is replaced with a second scan cell according to the static timing analysis that indicates the replaced first scan cell has a specific time margin in the scan mode. A first skew of the normal mode and a second skew of the scan mode are adjusted symmetrically in the first scan cell. The first skew and the second skew are adjusted asymmetrically in the second scan cell.